Modernized global navigation satellite system (gnss) receivers and commercially viable consumer grade gnss receivers

ABSTRACT

GNSS receivers and systems within such receivers use improvements to reduce memory usage while providing sufficient processing resources to receive and acquire and track E5 band GNSS signals directly (without attempting in one embodiment to receive L1 GNSS signals). Other aspects are also described.

This application claims the benefit of U.S. Provisional Patent Application No. 62/915,510, filed on Oct. 15, 2019, which application is incorporated herein by reference.

BACKGROUND

This disclosure relates to the field of Global Navigation Satellite Systems (GNSS) and in particular, this disclosure in one embodiment relates to GNSS receivers that use a modern L5 signal in the L5 frequency band. There are numerous GNSS systems that are available, including the United States' GPS (Global Positioning System), GLONASS, Galileo, Beidou, and regional systems that exist or may be deployed in the future. The United States' GPS system was initially available in only the L1 frequency band. Now, the United States' GPS system includes GNSS signals in the L5 band, and the Galileo system includes modernized GNSS signals (such as E5A and E5B) in the L5 band centered at 1191.79 MHz. The modernized GNSS signals in the L5 band provide certain advantages relative to GNSS signals in the L1 band, and some of the advantages are described below. However, the acquisition in a GNSS receiver of L5 band GNSS signals directly without the prior acquisition of L1 GNSS signals in the GNSS receiver has been considered too difficult and thus conventional GNSS receivers employ a technique in which the L1 GNSS signals are acquired first, and this acquisition provides information, such as time information and Doppler estimates, that is used to acquire GNSS signals in the E5 band. Thus, conventional GNSS receivers that support GNSS L5 signals use a radiofrequency front end that receives both L5 and L1 signals; this means there is a duplication of radiofrequency components in these GNSS receivers. Moreover, the conventional receivers must store and use pseudorandom noise (PRN) codes for both L1 and L5 GNSS signals.

SUMMARY OF THE DESCRIPTION

The various aspects described herein provide improvements that can allow a GNSS receiver to directly receive, acquire, process and use only L5 band GNSS signals in the GNSS receiver with greater sensitivity and reliability than by acquiring at narrowband L1, although in some embodiments these improvements can be used in conventional receivers that receive and process L5 band GNSS signals and one or more additional GNSS bands such as the L1 GPS band. These aspects can be implemented in various embodiments that can include GNSS receivers or portions of GNSS receivers or data processing systems (such as smartphones) containing such receivers or portions of such receivers and can include methods performed by such devices (e.g., GNSS receivers, etc.) and can include non-transitory machine readable media storing computer program instructions which when executed by a data processing system cause the data processing system to perform the one or more methods described herein.

One aspect of this disclosure relates to direct acquisition of L5 band GNSS signals. In other words, in this aspect, a GNSS receiver directly acquires L5 band GNSS signals without attempting to acquire time and frequency information from L1 band GNSS signals. The terms “direct acquisition” and “directly acquiring” are intended to mean that the GNSS receiver receives L5 band GNSS signals and acquires those signals to obtain time and frequency information derived from those signals without acquiring time and frequency information from L1 band GNSS signals. While cellular telephone assistance data (for time or phase locking for frequency as described in prior Snaptrack patents) may be used in the GNSS receiver, L1 band GNSS signals are not acquired and not used for a GNSS receiver that directly acquires L5 band GNSS signals. Thus, the GNSS receiver, when it directly acquires L5 band GNSS signals, acquires the L5 band GNSS signals to obtain time and frequency information from those signals without having the benefit of previously acquiring L1 band GNSS signals and without having the benefit of obtaining time or frequency information from L1 band GNSS signals.

Another aspect of this disclosure relates to sharing a cache memory between a set of one or more application processors (APs) and a GNSS processing system (or the sharing of other memory between the GNSS processing system and other processors on an SOC or integrated circuit). This aspect provides a solution for the often excessive memory requirements of acquiring L5 GNSS signals, particularly with methods that use discrete Fourier transform (DFT) computations. The one or more application processors (or other processors) and the GNSS processing system can be implemented together in a single monolithic integrated circuit (IC) on a single semiconductor substrate that can be referred to as a system on a chip (SOC) and the cache memory can also be on the same integrated circuit. In this aspect, the application processors (or other processors) share their cache memory (or other memory) with at least an acquisition engine (AE) of the GNSS processing system. This sharing can be limited, in one embodiment, to those situations in which the acquisition engine is initially acquiring GNSS signals (for example, a start with or without assistance data from a cellular telephone network). A portion of the cache memory, which can be L1 (level 1) or L2 (level 2) SRAM cache of the one or more application processors or other memory used by other processing systems, can be allocated to the acquisition engine for the acquisition phase, in response to a request for location data (such as a latitude and longitude) from an application program such as a map application or other application. The allocation may be prioritized or not by an operating system (OS) of the system or firmware on an IC depending on the location request; if the request for location is from a low priority background daemon application, then the allocation may be temporarily deferred until sufficient free memory in the cache memory is available. On the other hand, if the location request is from a map application that is the foreground application (and hence the display of the device shows the user interface of the map application to a user) then the allocation is prioritized. The portion to be allocated in one embodiment can be identified by determining which pages in the cache memory are not dirty and are stored in a backing store such as main DRAM or better yet non-volatile memory (such as flash memory). Such pages (e.g., not dirty and stored in a backing store) can be flushed/deleted immediately from the cache memory (or other memory) and then allocated to the AE for use in storing one or more of (for example): hypothesis data or generated GNSS PRN codes and/or their code spectrums from a DFT.

A method according to his sharing aspect can include the following operations implemented in a GNSS receiver: receiving, from one or more application processors on an integrated circuit a request to generate location data through use of a GNSS processing system on the integrated circuit, the GNSS processing system including an acquisition engine (AE) that is configured to acquire a plurality of GNSS signals, each of the GNSS signals transmitted from one of a constellation of GNSS space vehicles (SVs); identifying a portion of a cache memory (or other memory) on the integrated circuit and allocating, in response to the request to generate location data, the portion for use by the acquisition engine while the one or more application processors (or other processor(s)) are allocated a remaining portion of the cache memory (or other memory), the allocating performed by an operating system that executes on the one or more application processors or by firmware on the IC; and storing, by the acquisition engine or the one or more application processors, data related to GNSS signal acquisition processing in the allocated portion. The method in one embodiment can use static random access memory (SRAM) as the cache memory (or other memory) on the integrated circuit, and the acquisition engine can include ASIC (application specific integrated circuit) hardware logic for performing fast Fourier transform (FFT) operations such as discrete Fourier transform (DFT) operations using a decimation in time method and also using a decimation in frequency method. In one embodiment, the method can further include the operation of deallocating the allocated portion after the GNSS processing system begins to track GNSS signals that have been acquired from at least three (3) GNSS SVs, the deallocating occurring in response to acquiring, before a tracking phase, the GNSS signals from the at least three GNSS SVs. In one embodiment, the GNSS processing system includes a dedicated memory that is separate from the cache memory (or other memory) and is dedicated for use by the GNSS processing system. In one embodiment, a memory controller, coupled to the cache memory (or other memory), can include a first port controller to control access to the allocated portion for the acquisition engine and a second port controller to control access to the remaining portion of the cache memory (or other memory). In one embodiment, the acquisition engine performs an acquisition of GNSS signals from GNSS SVs and the acquisition comprises determining primary code phase and frequencies of received GNSS signals containing pseudo-random noise (PRN) codes to enable tracking of the GNSS signals to produce, as a result of the tracking, pseudoranges to the GNSS SVs. In one embodiment of the method, the allocated portion is to store one or more of: (1) pseudorandom noise codes of GNSS SVs or (2) hypotheses of identifiers of potentially acquired GNSS signals and hypotheses of their frequencies. In one embodiment of this method, the one or more application processors can generate, prior to an acquisition phase beginning, GNSS PRN codes and/or their code spectrums from DFTs for at least GNSS SVs that are in view of the system; in one implementation of this embodiment, these PRN codes and/or their code spectrums from DFTs can be generated and used immediately without storing these codes or alternatively these PRN codes and/or their code spectrums from DFTs can be generated and stored temporarily while being used during the acquisition and tracking phase. In one alternative embodiment, the one or more application processors can generate the GNSS PRN codes (or their code spectrums or both) and store them in the system's DRAM memory and then copy those codes into the cache memory (or other memory) prior to the beginning of the acquisition phase or in response to a request for location. In one embodiment, in order to conserve memory, the system can generate GNSS PRN codes and/or their code spectrums from DFTs for only healthy GNSS SVs that are in view.

In one embodiment, a system according to this sharing aspect can include the following components: a set of one or more application processors configured to execute an operating system (OS) and one or more application programs, the set of one or more application processors implemented in an integrated circuit; a set of one or more buses coupled to the set of one or more application processors, the one or more buses on the integrated circuit; a cache memory (or other memory) on the integrated circuit and coupled to the set of one or more buses and coupled to the set of one or more application processors to store data for use by the operating system or for use by the one or more application programs and other memory, such as high bandwidth modem memory or other memory used by one or more processors that are not in the set of one or more application processors, may also be on the IC and coupled to the one or more buses; a bus interface coupled to the set of one or more buses, the bus interface to couple the set of one or more application processors to dynamic random access memory (DRAM) which is external to the integrated circuit; a GNSS processing system implemented on the integrated circuit, the GNSS processing system comprising an acquisition engine (AE) and a tracking engine (TE), the GNSS processing system coupled to the cache memory (or other memory) through the one or more buses; and a memory controller coupled to the cache memory (or other memory) and to the set of one or more application processors and to the GNSS processing system, the memory controller to allocate a portion of the cache memory (or other memory) for use by the AE in response to one or more instructions from the operating system (or other software components) in order to allow GNSS signals to be acquired. In one embodiment, the cache memory can include static random access memory (SRAM) and the AE can include ASIC hardware logic for performing discrete Fourier transform operations using both a decimation in time method and a decimation in frequency method. In one embodiment, the memory controller can include a first port controller to control reading from and writing to the portion for the AE and a second port controller to control reading from and writing to a remaining portion of the cache memory (or other memory). In one embodiment, the memory controller can deallocate the portion of the cache memory (or other memory) used by the AE after the GNSS processing system begins to track GNSS signals that have been acquired from at least three GNSS SVs (but before a location data, such as a latitude and a longitude, is determined).

Another aspect that can help to alleviate memory usage in an L5 band GNSS receiver is the on-demand generation of GNSS PRN codes and/or their code spectrums from DFTs that are used to correlate to received GNSS signals during the acquisition phase. This on demand generation can produce GNSS PRN codes and/or their code spectrums from DFTs during the acquisition and tracking phases in one embodiment. For example, in one embodiment these codes can be generated but not stored during both the acquisition and tracking phases; in an alternative embodiment, the codes can be generated on the fly and on-demand and stored during both the acquisition and tracking phases, and once a location is determined these codes are no longer stored. In one embodiment, the codes and the code spectrums are generated before each correlation operation, once every 1 ms for every channel, and then the memory is overwritten for the next channel. There is no storage of codes or spectrums, just 1 memory that is temporarily reused. For example, with 24 channels being acquired the codes for the 24 channels are regenerated 24 times every 1 ms. It is temporarily stored in memory for the first stage of DFT performed during the frequency domain correlation algorithm.

Another aspect of this disclosure relates to an acquisition correlator that uses array processing. This array processing architecture can initially arrange the digitized GNSS sample data in, for example, rows in an array, where the rows are arranged in time in a baseband sample memory. DFT operations on the data can produce an output which can then be processed by inverse DFT operations without having to rotate or reformat or rearrange or transpose the data in the array prior to the inverse DFT operations. The data can be arranged such that each ALU in a set of multiple ALUs processes one row or one column in the array, thereby breaking the processing into discrete pieces that can be processed by each of the DFT ALUs such that each row or column can be computed in an atomic processing operation in one or a few processing clock cycles by a single DFT ALU which in one embodiment perform multiple DFT operations once instructed to do so. The baseband sample memory can be implemented in a circular buffer that contains the array of ordered data. In one embodiment, the processing operations can be DFT in place computations such that a row (or column) of input data is retrieved from memory and processed (using a DFT) and the output from this processing is then stored back in the same memory location as the input data (thus writing over the input data in those memory locations).

In one embodiment that can use an array processing architecture, a system for processing GNSS signals can include the following components: a radiofrequency analog to digital converter (ADC) to generate a digital representation of received GNSS signals; a baseband sample memory to store the digital representation of the received GNSS signals as digitized GNSS sample data in N2 rows (e.g., 1024 rows in one embodiment or 512 rows in another embodiment) and N1 columns (e.g., 20 columns in one embodiment or 40 columns in another embodiment), the array being stored in a row order in the baseband sample memory, and the row order containing the digitized GNSS sample data that was received over a time period (that includes a first time period and a second time period) such that a first row in the row order contains digitized GNSS sample data received during the first time period and a second row, which follows the first row in the row order, contains digitized GNSS sample data received during the second time period that follows, in time, the first time period, wherein the baseband sample memory is coupled to the RF ADC; and a set of arithmetic logic units (ALUs) configured to perform discrete Fourier transform (DFT) operations, the set of ALUs being coupled to the baseband sample memory and being configured to perform, in parallel and concurrently in time, N1 DFTs, wherein each of the N1 DFTs contains N2 points in the DFT and the outputs of the N1 DFTs are stored in a partial sample array, and wherein the set of ALUs are configured to then perform N2 DFTs, each of the N2 DFTs containing N1 points from the partial sample array, the N2 DFTs providing an output stored in a DFT result array that is arranged in column order. In one embodiment, the baseband sample memory is configured as a circular memory buffer that stores the digitized GNSS sample data. In one embodiment, the N1 DFTs use the same operations and same program control instructions for the set of ALUs to operate on different data. In one embodiment, the N2 DFTs are performed consecutively over time. In one embodiment, the circular sample memory buffer stores more than one frame of pseudorandom GNSS signals which is more than one millisecond. In one embodiment, the N1 DFTs and the N2 DFTs use a decimation in time method, and N1 is one of the integer values: 5, 10 or 20 or 40. In another embodiment, N2 is set such that N1×N2=20480 (or N1×N2 is greater than 20480). In one embodiment, a change from the row order to a column order avoids a reordering or transposition algorithm, and the change is produced by a combination of the N1 DFTs followed by the N2 DFTs that are configured to produce this change. In one embodiment, a GNSS code generator is configured to generate a GNSS codes spectrum, and the set of ALUs perform a set of DFTs on the GNSS PRN codes to provide a codes spectrum result data stored in a code spectrum memory in a column order. In one embodiment, the baseband sample spectrums are stored in special/dedicated memory, and recalculated every 1 ms, and the code spectrum is stored in general purpose variable memory and overwritten for every channel of every ms. In one embodiment, the set of ALUs can be configured to multiply the code spectrum result data by the sample output stored in the DFT result array to produce a product array. In one embodiment, the set of ALUs can be configured to perform an inverse DFT on the product array using a decimation in frequency method. In one embodiment, the inverse DFT can comprise: (1) in a first stage, N2 DFTs with conjugated inputs, each of the N2 DFTs containing N1 points, and (2) in a second stage that follows the first stage, N1 DFTs, each of the N1 DFTs containing N2 points. In one embodiment, the baseband sample memory can be a dual port memory allowing different processors or processes to simultaneously access different portions of the baseband sample memory. In one embodiment, the GNSS code generator can repeatedly generate a pseudorandom noise code for each GNSS SV in view every millisecond when it is needed during an acquisition phase and does not store a generated pseudorandom noise code (and/or its code spectrum from DFTs) after it is used, and the generated pseudorandom noise code can be used to generate the GNSS code spectrum. In one embodiment, the GNSS code spectrum is aligned in place in memory in both frequency and phase to match code phase and frequency shift hypotheses associated with the received GNSS signals. In one embodiment, this alignment can be performed by CORDIC hardware.

One or more embodiments of GNSS receivers described herein can perform one of the following methods that use a sequence of DFTs. In one embodiment, a method can include the following operations:

receiving GNSS signals;

digitizing the received GNSS signals and providing an output, from an analog to digital converter (ADC), of GNSS sample data which includes at least one of (1) GNSS sideband A sample data for a received GNSS signal and (2) GNSS sideband B sample data for the received GNSS signal;

computing at least one of (1) a first set of DFTs of the GNSS sideband A sample data to provide a first set of results and (2) a second set of DFTs of the GNSS sideband B sample data to provide a second set of results;

computing at least one of (1) a third set of DFTs of GNSS sideband A primary PRN code data which is adjusted for code Doppler and carrier Doppler prior to the third set of DFTs, the GNSS sideband A primary PRN code data including at least one of two components in the GNSS sideband A, the third set of DFTs providing a third set of results and (2) a fourth set of DFTs of GNSS sideband B primary PRN code data which is adjusted for code Doppler and carrier Doppler prior to the fourth set of DFTs, the GNSS sideband B primary PRN code data including at least one of two components in the GNSS sideband B, the fourth set of DFTs providing a fourth set of results;

computing at least one of (1) a first set of correlations using a DFT of the complex conjugate of a product of the first set of results and the complex conjugate of the third set of results to provide a fifth set of results and (2) a second set of correlations using a DFT of the complex conjugate of a product of the second set of results and the complex conjugate of the fourth set of results to provide a sixth set of results; and

integrating at least one of (1) the fifth set of results with at least one prior sum for the GNSS sideband A and (2) the sixth set of results with at least one prior sum for the GNSS sideband B, wherein the integrating includes at least one of (1) storing at least one new sum for GNSS sideband A components in a single hypothesis memory and (2) storing at least one new sum for GNSS sideband B components in the single hypothesis memory.

One implementation of this method can be summarized as (“case 1”):

-   -   1. computing FFT of a sideband A sample;     -   2. computing FFT of a sideband B sample;     -   3. computing FFT of at least one sideband A component primary         code adjusted for code Doppler and carrier Doppler (e.g. a range         of potential Dopplers to be searched);     -   4. computing FFT of at least one sideband B component primary         code adjusted for code Doppler and carrier Doppler;     -   5. computing correlations with inverse FFT (IFFT) of the product         of (a) the computed FFT from 1 (FFT of sideband A sample)         and (b) the computed FFT from 3 (FFT of sideband A component);     -   6. computing correlations with IFFT of the product of (a) the         computed FFT from 2 and (b) the computed FFT from 4.

This implementation can provide several advantages. For example, this implementation can have very few FFTs on the received sideband samples and can reduce or eliminate large data transfers normally required to move precomputed GNSS sample spectrums from memory (e.g. DRAM or non-volatile memory) to the frequency domain correlator array processor. The frequency domain correlation engine can be very efficient by re-using the engine at a reasonable clock speed while requiring a low or small memory footprint. For example, the frequency domain correlation engine can compute the primary codes and their spectrums (e.g., in operations 3 and 4 in summarized “Case 1” above) in place within the engine in a pipeline architecture described herein. Further, applying the code Doppler compensation and the carrier Doppler compensation to the in place generated codes (e.g., in operations 3 and 4 in summarized “Case 1” above) reduces the input (received) sample FFTs and also improves code Doppler accuracy.

There are numerous combinations and permutations of this implementation for acquisition of, for example, L5 GNSS signals. These combinations and permutations however can be less efficient than “Case 1” above because they require (relative to “Case 1”) faster processing clocks and/or more memory or because they have less acquisition sensitivity or require a longer time to acquire signals for a given signal strength. The use of the six (6) operations in “Case 1” can be retained but with permutations based on one or more of: (1) where and how code and carrier compensation are performed, for example: (a) carrier Doppler compensation can be a “wipe-off” of the received GNSS samples or an up-multiply on the locally generated (or precomputed) PRN code samples; or (b) code Doppler adjustments can be applied on the received GNSS samples (“input samples”) or the locally generated (or precompute) PRN code samples by a complex multiplication of code spectrums (see, e.g., Appendix 3) or by compensating the post correlation results and their integration in memory (see Appendix 1); (2) whether the code spectrums are locally generated in place in the acquisition engine (AE) or are precomputed and loaded into the AE based upon GNSS SVs in view; or (3) alternative hardware architectures (instead of decimation in time FFT and decimation in frequency FFT in sequence) such as parallel FFT kernels or higher radix kernels to reduce the number of processing clocks per FFT. The following 6 permutations are examples of the possible permutations.

Case 2 (switch code and carrier Doppler to samples: requires more input sample FFTs)

-   -   1. FFT of Sideband A adjusted for code and carrier Doppler     -   2. FFT of Sideband B adjusted for code and carrier Doppler     -   3. FFT of at least one A component primary code     -   4. FFT of at least one B component primary code     -   5. Correlations with IFFT of 1 and 3 products integrated into a         single hypothesis memory     -   6. Correlations with IFFT of 2 and 4 products integrated into a         single hypothesis memory

Case 2B (same as 2 with pre-computed code spectrums: requires more memory and data bandwidth)

-   -   1. FFT of Sideband A adjusted for code and carrier Doppler     -   2. FFT of Sideband B adjusted for code and carrier Doppler     -   3. Obtain precomputed FFT of at least one A component primary         code     -   4. Obtain precomputed FFT of at least one B component primary         code     -   5. Correlations with IFFT of 1 and 3 products integrated into a         single hypothesis memory     -   6. Correlations with IFFT of 2 and 4 products integrated into a         single hypothesis memory

Case 3 (same as 2 with code Doppler compensation post correlation)

-   -   1. FFT of Sideband A adjusted for carrier Doppler     -   2. FFT of Sideband B adjusted for carrier Doppler     -   3. FFT of at least one A component primary code     -   4. FFT of at least one B component primary code     -   5. Correlations with IFFT of 1 and 3 products adjusted for code         Doppler integrated into a single hypothesis memory     -   6. Correlations with IFFT of 2 and 4 products adjusted for code         Doppler integrated into a single hypothesis memory

Case 3B (same as 3 but with pre-computed code spectrums)

-   -   1. FFT of Sideband A adjusted for carrier Doppler     -   2. FFT of Sideband B adjusted for carrier Doppler     -   3. Obtain precomputed FFT of at least one A component primary         code     -   4. Obtain precomputed FFT of at least one B component primary         code     -   5. Correlations with IFFT of 1 and 3 products adjusted for code         Doppler integrated into a single hypothesis memory     -   6. Correlations with IFFT of 2 and 4 products adjusted for code         Doppler integrated into a single hypothesis memory

The following set of cases use the method described in the Appendix 1 that compute the FFTs of input sample sideband sample each msec at a number of frequencies like 0, 200, 400, 600, 800 and then the sample sideband A or B spectrum is approximated by choosing the closet sub kHz FFT and then shifting by +/−N samples to obtain a super kHz compensation. For example, 2450 Hz uses the 400 Hz FFT and shifts this FFT by +2 samples to get a combined 400 Hz+2 kHz Doppler compensation.

Case 4 (like method described in the Appendix 1)

-   -   1. At least one FFT chosen from a set of sideband A sample FFTs         adjusted for carrier Doppler at set of frequencies that cover a         one k-Hz range, the one FFT shifted by N samples to produce an         approximate carrier Doppler     -   2. At least one FFT chosen from a set of sideband B sample FFTs         adjusted for carrier Doppler at set of frequencies that cover a         one k-Hz range, the one FFT shifted by N samples to produce an         approximate carrier Doppler     -   3. FFT of at least one A component primary code adjusted for         code Doppler     -   4. FFT of at least one B component primary code adjusted for         code Doppler     -   5. Correlations with IFFT of 1 and 3 products integrated into a         single hypothesis memory     -   6. Correlations with IFFT of 2 and 4 products integrated into a         single hypothesis memory

Case 4A (like method 4 but with pre-computed code spectrums and code Doppler post correlation)

-   -   1. At least one FFT chosen from a set of sideband A sample FFTs         adjusted for carrier Doppler at set of frequencies that cover a         one k-Hz range, the one FFT shifted by N samples to produce an         approximate carrier Doppler     -   2. At least one FFT chosen from a set of sideband B sample FFTs         adjusted for carrier Doppler at set of frequencies that cover a         one k-Hz range, the one FFT shifted by N samples to produce an         approximate carrier Doppler     -   3. Obtain precomputed FFT of at least one A component primary         code     -   4. Obtain precomputed FFT of at least one B component primary         code     -   5. Correlations with IFFT of 1 and 3 products adjusted for code         Doppler integrated into a single hypothesis memory     -   6. Correlations with IFFT of 2 and 4 products adjusted for code         Doppler integrated into a single hypothesis memory

In some of the embodiments described herein, adjustments or compensations are made for one of or both of code Doppler and carrier Doppler. These adjustments can be performed independently and at different stages as described herein. Code Doppler adjustment is an adjustment to a locally generated code (or a precomputed code) or to a received GNSS sample code to adjust for Doppler effects on the code such as a primary GNSS PRN code; for example, during a search or acquisition phase multiple possible code Doppler adjustments can be made on the locally generated code or to the received GNSS sample code to search for and acquire a GNSS signal that has been effected by Doppler effects. Carrier Doppler adjustment is an adjustment to adjust for Doppler effects on a carrier frequency of a signal. The carrier Doppler is the observed frequency offset from the transmit frequency due to relative motion between the satellite and receiver and the offsets from nominal of the satellite and receiver oscillators. Code Doppler is the shift in the received code phase over time that is coherent with the carrier Doppler. At L5 there are 115 carrier cycles per code chips. Thus, the code Doppler in chips/second is the carrier Doppler divided by 115. So for a carrier Doppler of 4321 Hz, the received code phase will move 37.57 chips in one second. In order to receive weak signals, it is necessary to correlate the received signals against the receiver's replica signal for multiple primary code frames. This requires that each incoming code phase hypothesis must be shifted in accordance with the carrier Doppler hypothesis. This shift is referred to as the code Doppler.

Another aspect of the disclosure involves the use of the primary and/or secondary code in E5 GNSS signals from one GNSS SV to derive code phase data or time data based on those GNSS signals and to then use that information to make estimates about code phases for other GNSS signals from other GNSS SVs to acquire code phases for the other GNSS signals from the other GNSS SVs. In this aspect, the GNSS receiver can employ a processing epoch that can be less than the 1 ms GNSS PRN code epoch and can be offset from the 1 ms GNSS PRN code epoch, and the GNSS receiver can use that processing to attempt to coherently integrate prior to acquiring the code phases for the other GNSS signals; for example, the GNSS processing system in the GNSS receiver can retrieve, every 0.25 milliseconds, a full 1 millisecond (ms) of digitized GNSS sample data from a circular memory buffer and perform a set of DFTs and inverse DFTs on the retrieved data to coherently integrate for each frequency bin and then repeat this VFFDC process on the next processing epoch, with each processing epoch being 0.25 milliseconds or some other fraction of a code epoch that is, in one embodiment, 1 ms long. This can allow the GNSS receiver to use the 1 millisecond data from the circular buffer repeatedly over multiple processing epochs to attempt to coherently integrate the other GNSS signals using the information obtained by previously acquiring the primary or secondary code phase of at least one of the GNSS signals. In this example, satellite codes are searched in alignment with the approximate time bin in which they are expected to be received, such that sub-millisecond coherent cancellation losses due to phase reversals associated with the secondary code are reduced. In another embodiment, the receiver clock may already be sufficiently accurate (much less than 1 ms of error) and an a priori position may be sufficiently well-known to allow for processing of all GNSS signals in this precise-time acquisition mode.

Another aspect of this disclosure involves the use of only a subset of the two or four components of the GNSS signals (a selected component) to first acquire that subset (such as only one of the four components) during coarse time acquisition and then acquire the remaining components. In one embodiment, this selected component is selected based on a lowest probability of signal change due to sign or phase reversals due to the coding scheme used in that selected component. In the case of Galileo's E5 GNSS signals, the E5BI component has the lowest probability of signal change due to sign or phase reversals and thus can be used as the selected component to perform a coarse or precise time acquisition before attempting to acquire and/or track the remaining components in the Galileo GNSS signals. This use of only a subset of the components can be done initially when beginning an acquisition (such as a coarse time acquisition) or as a fallback mode of operation after a conventional acquisition has failed or as a method to acquire a stronger satellite more quickly as the number of correlations is reduced, allowing a portion of a GNSS acquisition engine to search a large frequency space for many SVs more quickly and with lower power than if more GNSS signal components are employed.

Another aspect of this disclosure involves the mitigation of the impact of interference from certain known strong interferers such as the aeronautical radio navigation (ARN) signals that are commonly present around, for example, airports or military bases. The ARN signals, such as signals from a tactical air navigation system (DME/TACAN), are often strong pulsed signals that are well above a noise floor while GNSS signals are normally below the noise floor. Moreover, the ARN signals can cause interference with GNSS in the L5 band. This interference in one embodiment can be mitigated by detecting a signal source above the noise floor (for example, detecting a signal that is above a predetermined threshold which can be several dB above a noise floor) and then removing the signal in the frequency domain. The interfering signal can be identified during the signal acquisition phase using the DFT array processing that is described herein, and then the interfering signal can be processed through an FIR (Finite Impulse Response) filter to remove the interfering signal before time domain correlation processing. Alternatively, the frequencies with strong interference can be observed in the input data spectrums as the spectrum of the inputs samples is performed every msec and at each of the upper and lower sidebands. Another aspect of this disclosure involves the mitigation of the impact of interference from certain known interferers by narrowing the processing bandwidth of the radio receiver, focusing on one of the two sidebands E5a or E5b depending on the location of the interferer. Once the general interference frequency location is determined using DFT array processing detection or other methods, various analog and mixed-signal techniques can be employed to reduce the effects of interference prior to quantization. In one case, the radio filtering can narrow the effective radio bandwidth from 52 MHz to 26 MHz or smaller. Although this may introduce a small performance penalty, it allows the receiver to operate with larger interference margin. In another case, a configurable notch can be placed at an effective frequency location during the IF band-pass filtering of the radio architectures of FIGS. 4D, 4F and 4J. Furthermore a notch can also be placed at an effective frequency location during the low pass filtering of the architectures shown in FIGS. 4B, 4D, 4F. In yet another case, the IF frequency and/or the sampling frequency of the radio architecture of FIG. 4J can be modified so that the frequency plan immunity to aliased interference in improved.

Another aspect of this disclosure relates to methods to reduce memory usage by calculating but not storing outputs from certain DFTs. This method can reduce the size of the integration or hypothesis memory by eliminating storage of selected outputs from the DFT computations. In one embodiment, the outputs are evaluated to determine whether to save the outputs. This can be employed when the DFT methods are used to perform the correlations. In this case, the DFT produces correlation results at all the code hypotheses over one millisecond. In case the epoch location uncertainty is far less a millisecond, the full range, then only a portion around the estimated location needs to be integrated and saved.

The aspects and embodiments described herein can include non-transitory machine readable media that store executable computer program instructions that when executed can cause one or more data processing systems to perform the methods described herein when the computer program instructions are executed by the one or more data processing systems. The instructions can be stored in nonvolatile memory such as flash memory or dynamic random access memory which is volatile or other forms of memory.

The above summary does not include an exhaustive list of all embodiments in this disclosure. All systems and methods can be practiced from all suitable combinations of the various aspects and embodiments summarized above, and also those disclosed in the Detailed Description below.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawings will be provided by the Office upon request and payment of the necessary fee.

The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements.

FIG. 1 is a block diagram which shows an example of a data processing system which includes a GNSS processor and one or more application processors.

FIG. 2 is a block diagram that shows an example of an embodiment which includes a GNSS processing system and one or more application processors and a cache memory.

FIG. 3 is a flowchart which illustrates a method according to one embodiment for sharing a cache memory between one or more application processors and a GNSS processor.

FIG. 4 shows an example of a front-end of a GNSS receiver which digitizes received GNSS signals according to one embodiment.

FIG. 4A shows an example of a convention or nomenclature that is used to describe a radio portion of a GNSS receiver.

FIG. 4B shows an example of a conventional IQ receiver architecture that can be used in a GNSS receiver.

FIG. 4C shows an example of the frequency plan of the receiver architecture shown in FIG. 4B.

FIG. 4D shows an example of a GNSS receiver according to one embodiment.

FIG. 4E shows an example of the frequency plan of the receiver architecture shown in FIG. 4D.

FIG. 4F illustrates a variation of the GNSS receiver shown in FIG. 4D.

FIG. 4G shows an example of the frequency plan of the receiver architecture shown in FIG. 4F.

FIG. 4H shows an example of a subsampling arrangement that can be used in one or more embodiments of the inventions described herein.

FIG. 4I shows an example of a frequency plan that can be used in the subsampling architecture shown in example shown in FIG. 4H.

FIG. 4J shows an example of an architecture of a GNSS receiver that can use aspects of the arrangement in FIG. 4H.

FIG. 4K shows an example of the frequency plan of the receiver architecture shown in FIG. 4J.

FIG. 4L shows an example of an embodiment of a GSSS receiver that is configured to fold sidebands of GNSS signal onto each other.

FIG. 4M shows another example of an embodiment of a GSSS receiver that is configured to fold sidebands of GNSS signal onto each other.

FIG. 4N shows an example of another embodiment of a GSSS receiver that is configured to fold sidebands of GNSS signals onto each other; FIG. 4O shows a Galileo E5 signal frequency spectrum, and FIG. 4P shows a Galileo E5B signal frequency spectrum.

FIGS. 5A and 5B show an example of a method according to one embodiment which uses array processing with DFTs.

FIG. 6 is a block diagram which illustrates a frequency domain correlator architecture that uses array processing according to one embodiment.

FIG. 7 shows, in block diagram form, an example of processing components to perform array processing according to one embodiment.

FIG. 8 shows, in block diagram form, an example of further processing components to perform array processing according to one embodiment.

FIGS. 9A, 9B, 9C and 9D show an example of processing components and a method that can be used to generate a PRN code spectrum for use in the array processing architecture shown in FIGS. 6, 7, and 8.

FIG. 10 shows an example of components which can be used in one embodiment of a GNSS receiver.

FIG. 11 is a flowchart that shows a method according to one embodiment.

FIG. 12 shows an example, in block diagram form of an L5 WB band only GNSS receiver.

FIG. 13 shows an example of an embodiment that uses a selected signal in a set of GNSS signal components to initially acquire GNSS signals in certain cases.

FIG. 14A shows an example of an embodiment of the front end processing flow in a GNSS receiver.

FIG. 14B shows a timing diagram for an embodiment that uses a series of captured GNSS signals that are stored in a buffer and then processed to accumulate a codephase hypothesis.

FIG. 14C shows a coarse time acquisition processing timeline according to one embodiment.

FIG. 14D shows a precise time acquisition processing timeline according to one embodiment.

FIGS. 14E and 14F show examples of FFT processor architectures according to one embodiment.

FIG. 14G is a flowchart that shows a method that can be used in a frequency domain correlator, particularly a correlator that uses an array processor.

FIG. 14H shows another example of an FFT processor architecture according to one embodiment.

FIG. 14I is a flowchart that shows a method that can be used in a frequency domain correlator, particularly a correlator that uses an array processor.

FIG. 14J is a flowchart that shows a method that can be used in a frequency domain correlator, particularly a correlator that uses an array processor.

FIG. 14K is a block diagram of a system on a chip (SOC) that includes a GNSS receiver and one or more application processors according to one embodiment.

FIG. 14L is a flowchart that shows a method that can be used, during coarse time acquisition mode, in a frequency domain correlator, particularly a correlator that uses an array processor.

FIG. 14M is a flowchart that shows a method that can be used, during precise time acquisition mode, in a frequency domain correlator, particularly a correlator that uses an array processor.

FIG. 14N shows an example of an arrangement of hypothesis memory for use in non-coherent integration in coarse time mode during code phase acquisition of GNSS signals.

FIG. 14O shows an example of an example of an arrangement of hypothesis memory for use in coherent integration in precise time mode (when time is known within, for example, 0.5 ms) during code phase acquisition of GNSS signals.

FIG. 14P is a flowchart that shows a method according to one embodiment to configure hypothesis memory.

FIG. 15A is a flowchart that shows a method according to one embodiment to mitigate interference, such as ARN interference.

FIG. 15B is a flowchart that shows another method according to one embodiment to mitigate interference, such as ARN interference.

FIG. 16A shows a processing flow according to one embodiment that uses rotation or interpolation with DFTs to acquire GNSS signals.

FIG. 16B shows a processing flow according to another embodiment that uses rotation or interpolation with DFTs to acquire GNSS signals.

FIG. 16C shows a processing flow according to another embodiment that uses rotation or interpolation with DFTs to acquire GNSS signals.

FIG. 17 shows an example of a method that can reduce power consumption by acquiring a set of GNSS signal components during an acquisition phase and then tracking with only a subset of those acquired components.

DETAILED DESCRIPTION

Various embodiments and aspects will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative and are not to be construed as limiting. Numerous specific details are described to provide a thorough understanding of various embodiments. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments.

Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in conjunction with the embodiment can be included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The processes depicted in the figures that follow are performed by processing logic that comprises hardware (e.g. circuitry, dedicated logic, etc.), software, or a combination of both. Although the processes are described below in terms of some sequential operations, it should be appreciated that some of the operations described may be performed in a different order. Moreover, some operations may be performed in parallel rather than sequentially.

One aspect of the embodiments described herein relates to the sharing of cache memory between one or more application processors and a GNSS processing system. Before describing these sharing embodiments, a description of a prior architecture in the prior art will be provided with reference to FIG. 1. FIG. 1 shows a system 10 that includes one or more application processors 12 and a GNSS processor 20 that are coupled through a bus 14 which is also coupled to system main memory which is the dynamic random access memory (DRAM) 24. The system 10 includes one or more input/output (110) devices 26 such as, for example, one or more touchscreens, speakers, microphones, and one or more sensors such as cameras, face detect sensors, etc. The system 10 also includes a cellular telephone modem and processor 16 which can include its own cache memory which can be SRAM 16A. The cellular telephone modem and processor 16 is coupled to the cellular telephone RF components 17 to receive cellular telephone signals through the antenna 18. The GNSS processor 20 is configured to receive and process GNSS signals in both the L1 and L5 bands. Moreover, the GNSS radiofrequency (RF) components 21 are configured to receive GNSS signals in both the L1 and L5 bands through the antennas 22A and 22B, and the GNSS RF components 21 include one or more RF mixers and RF to intermediate frequency downconverters and do include an RF local oscillator. These GNSS signals are processed by the GNSS processor 20 which includes its own dedicated processor memory as part of the GNSS processor 20. The GNSS processor does not use or share the cache memory 12A which is used by the one or more application processors 12 using techniques known in the art for utilizing a cache memory. The GNSS processor receives and processes GNSS signals and provides location outputs, such as latitude and longitude outputs, to the one or more application processors 12 through the bus 14. The GNSS processor receives and processes the GNSS signals without utilizing the cache memory 12A and requires two separate GNSS antennas 22A and 22B and two separate GNSS RF paths starting at the two GNSS antennas 22A and 22B.

FIG. 2 shows an example of a system in which the cache memory in the system is shared between one or more application processors and a GNSS processing system. The system 50 shown in FIG. 2 includes a system-on-a-chip (SOC) 52 that includes one or more application processors 66 and a cache memory 70 and a GNSS processing system 68. In one embodiment, the SOC 52 can be a single monolithic semiconductor device embodied in the substrate of an integrated circuit that includes all of the components shown within the perimeter of the SOC 52 as shown in FIG. 2. The SOC 52 can include a memory controller 72 which controls access to the cache memory 70 (or other memory) which is coupled to both the one or more application processors 66 and to the GNSS processing system 68. Thus the memory controller 72 can arbitrate usage of the cache memory 70 to allow the GNSS processing system 68 and the one or more application processors 66 to both use the cache memory which in one embodiment can be implemented as SRAM memory. In one embodiment, the memory controller 72 can allocate one portion of the cache memory 70 for use by the GNSS processing system and allow the remaining portion of the cache memory 70 to be used by the one or more application processors 66. In one embodiment, the cache memory 70 can be used to store program code or program instructions as well as data which is operated on by the processing systems. As further described below, when the acquisition engine of the GNSS processing system 68 is acquiring GNSS signals, the acquisition engine can use the cache memory to store, for example, hypotheses in hypothesis memory used during the acquisition phase or can use the cache memory 70 to store generated PRN codes (and/or their code spectrums from DFTs) for the GNSS signals. The GNSS processing system 68 can be coupled to the one or more application processors 66 through the bus 74. The one or more application processors 66 and the GNSS processing system 68 can also be coupled to the cellular telephone modem and processor 76 through the bus 74. In one embodiment, the bus 74 is a set of buses on the SOC 52. The SOC 52 also includes a bus interface 78 which allows the SOC 52 to be coupled to a system bus 54 which is exterior to the SOC 52. There are several other components which are exterior to the SOC 52, and they include the GNSS radiofrequency components 63 which in the example shown in FIG. 2 are configured to operate only in the L5 wideband (WB) band to receive and process only L5 wideband (WB) GNSS signals in the embodiment shown in FIG. 2. The terms or phrases L5 WB band or L5 WB signals or L5 WB GNSS are meant to include or refer to the modernized GNSS signals and modernized GNSS systems (e.g., constellations of SVs and receivers) that operate at a modernized frequency band centered at 1191.795 MHz and have a chipping rate of 10.23 MHz or significantly higher than the legacy chipping rate or GPS L1 of 1.023 MHz and these modernized GNSS systems include, for example, the US L5 GPS system, the European E5 Galileo system, the Chinese Beidou/Compass B2 system, Glonass K2, and QZSS. The cellular telephone modem and processor 76 is coupled to a cellular telephone radio frequency component 64 to receive cellular telephone signals and to transmit cellular telephone signals. The DRAM 56 is coupled to the bus 54 and can store user data and application programs and an operating system. In addition, the system 50 can also include nonvolatile memory 57, such as flash memory, which is in addition to the DRAM 56. The nonvolatile memory 57 can store user data and application programs and the operating system for the system 50. The system 50 can also include various input/output devices which can be interfaced with the remainder of the system through one or more I/O controllers 58. The input/output devices can include one or more sensors 62 and other input/output devices 60. For example, the sensor may include one or more of a 3-axis accelerometer, 3-axis gyro, ambient light sensor (ALS), barometric pressure sensor, magnetometer, one or more cameras, etc. In addition, the system 50 can include other radiofrequency components 62 such as Bluetooth, Wi-Fi, etc. A method for operating system 50 will now be provided while referring to FIG. 3.

The system 50 in operation 101 (shown in FIG. 3) can receive a request from an application to determine a location. This request can be either from a foreground application or from a background application. For example, a map application which is in the foreground and therefore displaying a user interface of a map to the user requests a location, and this request can cause the GNSS processing system 68 to be activated. Alternatively, a daemon background process can make a request for a location. The nature of the request can determine a priority for the memory controller 72 in determining how and when allocate a portion of the cache memory 70 for use by the GNSS processing system 68. For example, a foreground application request for a location can make the allocation of a portion of the cache memory 70 for use by the GNSS processing system 68 a high priority task causing the portion to be allocated as quickly as possible in some embodiments. Alternatively, a background application request for a location can make the allocation of a portion of the cache memory 70 by the memory controller 72 a deferred process or task, giving the memory controller 72 more time to allocate a portion of the cache memory 70.

In operation 103, the GNSS processing system 68 can receive assistance data from, for example, the cellular telephone modem and processor 76. In one embodiment, a satellite almanac or other data source about satellites in view over a period of time can be received by the system 50 and stored for later use by the GNSS processing system 68. Based upon the satellites or space vehicles (SVs) that are in view (from, for example a received satellite almanac), the GNSS processing system 68 can generate pseudorandom noise (PRN) codes and/or their code spectrums from DFTs (e.g. see code spectrum memory 263 in FIG. 6) for those GNSS SVs in view in operation 105. In one embodiment, the GNSS processing system 68 can generate on-demand these codes and use these codes without storing them during the acquisition and tracking phases for processing GNSS signals. In another embodiment, the GNSS processing system 68 can generate on-demand these codes and/or their code spectrums from DFTs (e.g. see code spectrum memory 263 in FIG. 6) and use these codes and/or their code spectrums from DFTs (e.g. see code spectrum memory 263 in FIG. 6) but also store them during the acquisition and tracking phases for processing GNSS signals, but as soon the tracking phase is finished these codes are no longer stored. In one embodiment, the code spectrum (generated from the GNSS PRN codes of GNSS SVs in view) can be generated but not stored (beyond about 1 millisecond) and the code spectrum can be repeatedly generated again and again for every millisecond (ms) of the GNSS sample data that is received and stored (in, for example, a circular memory buffer); thus in a first ms, a code spectrum is generated by applying a code Doppler (e.g. time shift) and a carrier frequency Doppler adjustment (see, for example, FIG. 6 and FIG. 9D) to the generated GNSS primary PRN code prior to the DFTs (by, for example, DFT ALUs 261) and then in a second ms (the next millisecond after the first ms) a new code spectrum is generated. A benefit of applying the code Doppler and carrier frequency adjustment prior to generating the code spectrum (through, for example, the DFT ALUs 261 in FIG. 6) is that the code spectrum cannot be precomputed or even used on subsequent milliseconds because the code Doppler rate for E5 GNSS signals is high and thus the code Doppler should be shifted for each millisecond interval to maintain high correlation. In one embodiment, the code Doppler shifted code spectrums can be stored for short periods of time if memory is available to reduce use of computational resources. The on-demand generation of these codes (which continues until a location data is determined) without long-term storage or without any storage can reduce the amount of memory used by the GNSS processing system 68. Similarly, the sharing of the cache memory 70 with the one or more application processor 66 can also reduce the usage of memory by the GNSS processing system 68. In operation 107, a portion of the cache memory, such as SRAM memory, on the integrated circuit containing the GNSS processing system and the one or more application processors can be allocated by, for example the memory controller 72. This can then allow the acquisition engine in the GNSS processing system 68 to use the allocated portion during at least the acquisition phase.

The acquisition phase typically involves determining the frequencies and primary code phases of acquired PRN codes and the identifiers of the satellites that have transmitted those acquired PRN codes. The PRN codes are acquired when a correlation operation indicates a match between a locally generated PRN code and a received PRN code. In one embodiment, in operation 109, the acquisition engine in the GNSS processing system uses the allocated portion for storage of hypothesis data and/or GNSS PRN codes. Then in operation 111, the acquisition engine acquires one or more GNSS signals to allow a tracking engine in the GNSS processing system to track acquired GNSS signals to thereby determine pseudoranges to the GNSS SVs that have transmitted the GNSS signals that have been acquired by the acquisition engine. In one embodiment, in operation 113, the portion of the cache memory can be deallocated after the tracking phase begins. For example, the memory controller 72 can deallocate the portion that contained the hypothesis data while retaining the GNSS PRN codes and/or their code spectrums from DFTs (e.g. see description of code spectrum memory 263 below) for tracking if they are stored in the cache memory. In an embodiment in which the PRN codes and/or their code spectrums from DFTs (e.g. see description of code spectrum memory 263 below) are not stored but rather are generated on the fly during use, then the deallocation of the portion of the cache memory used by the acquisition engine can be a complete deallocation freeing up the cache memory 70 for use by the one or more application processor 66. Then in operation 115, the GNSS processing system 68 can derive pseudoranges and can use the pseudoranges and ephemeris data for the GNSS SVs to determine location data for the system, such as system 50.

In one embodiment, the GNSS processing system 68 can include a dedicated memory that is separate from the cache memory 70 and is dedicated for use by the GNSS processing system. In one embodiment, the memory controller 72 can include a first port controller to control reading from and writing to the portion for the acquisition engine and a second port controller to control reading from and writing to a remaining portion of the cache memory 70. In one embodiment, the generation of GNSS PRN codes and/or their code spectrums from DFTs can be performed only for healthy GNSS SVs that are in view at the time of the request for location data (based upon, for example, information about SV health and about SVs in view in a received satellite almanac). This selective generation of GNSS PRN codes and/or their code spectrums from DFTs without saving the codes (in memory outside of registers and buffers in the pipeline processing logic) after the tracking phase or during the acquisition and tracking phases can reduce memory usage by the GNSS processing system. The pipeline processing logic can include registers and buffers that store the codes and code spectrum momentarily during one or a few clock cycles. In one embodiment, the GNSS processing system 68 can use the array processing architecture described below, such as the architecture shown in FIGS. 6, 7, 8, and 9 to provide additional reduction in memory usage by the GNSS processing system by, for example, using in place DFT algorithms.

In one embodiment, the operating system (or processor firmware) can perform the allocation of the portion of the cache memory for the GNSS processing system based upon information (which can be referred to as metadata) about the data stored in the cache memory. For example, this metadata can indicate whether or not the data stored in the cache memory, prior to the allocation of a portion of the cache memory for use by the acquisition engine, is “dirty” (e.g., it has been changed while stored in the cache memory) or whether it already exists in storage in a backing store such as in nonvolatile storage (e.g., flash memory) or even DRAM memory. For example, if the cache memory, prior to the allocation of a portion of the cache memory for use by the acquisition engine, is storing computer program instructions or code that is already stored in nonvolatile storage and these computer program instructions have not been modified while it is within the cache memory, then that portion of the cache memory can be allocated to the acquisition engine without having to write the data in the portion out to DRAM memory or out to nonvolatile storage. This can allow the operating system (or processor firmware) to quickly flush a portion of the cache memory so that it can be quickly allocated for use by the acquisition engine of the GNSS processing system. In the example shown in FIG. 2, the GNSS processing system shares a memory (e.g. cache memory 70) with one or more application processors (APs); in an alternative embodiment, the GNSS processing system can share other memory with other processing systems (e.g. one or more other processors) that are on the IC. In this alternative embodiment, the GNSS processing system shares the other memory and does not use or share the one or more AP's cache memory. The other memory and the GNSS processing system and the other processing systems can be all on the same IC (e.g. an SOC that also includes the one or more APs and the one or more AP's cache memory). The other processing systems can be one or more modem processor(s) or graphics processor(s) or codec(s) that use the other memory that is separate from the cache memory used by the one or more APs, and this separate, (on-chip) other memory can also be two-port (“dual port”) memories that support high bandwidth data access (both reading and writing). A memory controller can, as described herein, arbitrate access to the other memory when both the GNSS processing system and the other processing system(s) are seeking concurrent access to the other memory. In one implementation of this alternative embodiment, the other memory can be processor local storage of one or more of the other processing systems, and these one or more of the other processing systems use their processor local storage exclusively except when the GNSS processing system needs to use that processor local storage.

Another aspect of this disclosure involves the use of an array processing architecture with DFTs to acquire and track GNSS signals from, for example, E5 GNSS SVs. This aspect is shown in FIGS. 4, 5A, 5B, 6, 7, 8, 9A-9D, and 10 and will now be described with reference to those figures. FIG. 4 shows an example of a portion 150 of a GNSS receiver that receives GNSS signals and stores them in a two dimensional (2D) baseband sample array after an analog-to-digital conversion. The GNSS receiver can include a GNSS radiofrequency (RF) front end 153 which receives GNSS signals through an antenna 151 that is coupled to the GNSS RF front-end 153. In one embodiment, the GNSS RF front end 153 receives only L5 WB GNSS signals.

FIG. 12 shows an example of the components and architecture which can be used in one embodiment of the GNSS radio receiver 153. As shown in FIG. 12, the GNSS receiver includes an RF front end module 701, an RF and mixed signal section 702, and a digital front end 703 that can be both integrated in an ASIC (which can be part of the SOC 52); the RF front end module 701 can be separate from the ASIC that contains the digital front end 703 and possibly the RF and mixed signal section 702. The RF front end module 701 can be implemented in an RF integrated circuit (IC) that is coupled to a GNSS antenna 707 that is tuned to receive L5 WB GNSS signals; the GNSS antenna 707 is normally off chip and thus not on the RF IC. The GNSS antenna 707 receives the GNSS signals and provides those signals to a bandpass filter 709 that is configured to pass signals centered at 1192 MHz with a bandpass bandwidth of 51 MHz, and thus GNSS signals between about 1166.5 MHz and 1217.5 MHz pass through the bandpass filter 709. The output of bandpass filter 709 is coupled to LNA 711 to provide the bandpass filtered GNSS signals to LNA 711. In one embodiment, the GNSS antenna 707 is tuned to receive only L5 WB GNSS frequency signals. The RF front end module can include a low noise amplifier (LNA) 711 that is tuned for only the L5 WB frequency band and thus is optimized to receive that L5 WB band and no other LNA to receive other GNSS signals (e.g. L1 GPS) is present in the GNSS receiver shown in FIG. 12. The output of the LNA 711 can be filtered by a band pass filter 713 and the output from that filter 713 is amplified in amplifier 715 on the ASIC that contains the RF and mixed signal section 702 and then an ADC 717 converter generates the digitized GNSS sample data that is then processed to generate, in one embodiment, two streams of digitized GNSS sample data: one for GNSS sideband A and the other for GNSS sideband B. The clock generation phase lock loop 719 and the clock dividers 723 and 725 generate clock signals used by the ADC 717 and by the CIC decimators 721 and 729 to generate digitized GNSS sample data for up to four GNSS signal components (e.g. E5AI, E5AQ, E5BI, and E5BQ). The downconverter 727 separates the I and Q signals, and the sideband split downconverter 731 separates the upper sideband from the lower sideband to provide the GNSS sample data be stored in a baseband sample memory such as baseband sample memory 253 in FIG. 6. In one embodiment of the GNSS receiver shown in FIG. 12, the GNSS receiver has a direct connection from an LNA (e.g. LNA 711) through one or more filters (e.g. bandpass filter 713) and/or one or more gain stages (e.g. amplifier 715) to the analog to digital converter (ADC 717), and this GNSS receiver has no RF mixers, and thus there are no RF mixers in the RF front end module 701 and no RF mixers in the digital front end 703. Moreover, this GNSS receiver has no RF reference local oscillator (e.g., no phase lock loop) and there is no down conversion (in frequency) in the RF signal path prior to the ADC (e.g. ADC 717). In conventional GNSS receivers, an RF local oscillator and one or more RF mixers are used to perform RF down conversion in the RF signal path prior to the ADC.

Referring back to FIG. 4, the output from the GNSS RF front end 153 can be provided to a radio frequency (RF) analog-to-digital converter (ADC) 155 which can generate digitized GNSS sample data from the digitized GNSS signals. The output from the RF ADC 155 can be stored in one embodiment in a baseband sample array, such as the baseband sample array 157 shown in FIG. 4. In one embodiment, the baseband sample array 157 can have N2 or more rows and N1 columns to provide an N2 by N1 array (N2×N1). The number of samples in the array can be configured such that they satisfy the Nyquist criteria for providing a sufficient number of samples. If in one embodiment N1=20 and N2=1024, then there are 20,480 samples over time (e.g., 1 millisecond or slightly more than 1 ms such as 1.05 ms) which can satisfy the Nyquist criteria. The RF ADC 155 is configured to repeatedly, over time, receive and convert analog samples from the GNSS RF front end 153 into digitized GNSS samples that are stored in the array 157. For example, the RF ADC can repeatedly convert samples of GNSS signals and cause them to be stored in the array 157. In one embodiment, the array 157 can be implemented as a circular memory buffer that stores the digitized samples; the circular memory buffer, as is known in the art, can use a write pointer to indicate the next write location into the array and a read pointer to indicate the next read location. The write pointer is used when the ADC 155 provides an output to be stored into the circular buffer, and the read pointer is used when the ALUs read the next set of inputs for processing. The array 157 can provide data to a set of arithmetic logic units (ALUs) 159 that are configured to perform DFTs and inverse DFTs to provide acquisition and, in one embodiment, tracking of GNSS signals, and FIGS. 6, 7, 8, and 9 show an embodiment for the ALUs 159. Prior to describing these ALUs 159, a method for using this array processing architecture will now be provided while referring to FIGS. 5A and 5B. The method shown in FIGS. 5A and 5B can use the array processing architecture shown in FIG. 6.

In operation 201 shown in FIG. 5A, the digitized GNSS sample data is stored in a two-dimensional memory array which can be a circular buffer (such as the memory 253 in FIG. 6) containing slightly more than one 1-millisecond frame of GNSS signal data such as 1.05 or 1.25 milliseconds of GNSS signal data. One frame of E5 GNSS PRN code data in the GNSS signal is 1.0 milliseconds in length. The additional memory beyond one millisecond can be determined by the time needed to compute the spectrums (via DFTs) of the input data before the data is overwritten. Thus, a faster DFT means a shorter additional time beyond one millisecond is sufficient. In one embodiment, the data in the memory array is formatted such that successive rows contain successive time samples. For example, the first row can contain samples through time periods t1 to t20 and the second row can contain samples through time periods t21 to t40. The array 157 shown in FIG. 4 shows an example of such an array which can, in one embodiment, be stored in the baseband sample memory 253 in FIG. 6. The purpose of these optimizations is to minimize, in one embodiment, the number of clocks needed to perform the correlation process implemented using frequency domain operations: that is, that the inverse DFT of the product of the input sample DFT times the complex conjugate of the code samples adjusted for the carrier frequency produces the correlation of the input samples at all the possible code hypotheses at the carrier frequency hypothesis. This single step as defined here is referred to as the very fast frequency domain correlation (VFFDC) which is a form of frequency domain correlation (FDC). Optimizing the flow of data through these operations reduces the number of clock periods required to perform the correlation. The advantage being that for a given system clock, the number of carrier frequency estimates or hypotheses that can be checked in one millisecond is increased. Also, reducing the clocks means that the system timing requirements can be relaxed, allowing a more reliable chip design, or a design than can operate at a lower voltage to reduce power consumption, or a faster clock to achieve more throughput. Alternatively, a method of performing FDC can be employed that requires more clocks, but then a higher clock frequency is required. The clocks required to perform FDC can be reduced by using a matrix configuration (such as array 157) whereby the output of the sample and code spectrums is ordered so that the clocks required to perform the IDFT of the complex conjugate of the product can be reduced. Then in operation 203, a GNSS processing system, such as the GNSS processing system shown in FIG. 6 or the GNSS processing system 68 shown in FIG. 2, can retrieve the GNSS baseband data from the two-dimensional memory array and load the retrieved GNSS baseband data into a set of DFT ALUs. For example, the set of DFT ALUs can be a set of four ASIC hardware DFT ALUs in an acquisition engine, where each of the DFT ALUs can perform 20 parallel DFT operations in each DFT ALU in response to a single program instruction. In one embodiment, the set of DFT ALUs can be the DFT ALUs 255 shown in FIG. 6. In operation 205, the GNSS processing system can generate PRN code data (or alternatively retrieve from storage such PRN code data) and/or their code spectrums from DFTs for each expected GNSS signal source such as for each set of E5 or L5 or B2 GNSS SVs that are known to be in view. Once the PRN code data is generated it can be shifted in time and shifted by frequency and also up sample interpolated (e.g., padding the last bit in the code by adding a zero) to generate code data that is operated on by a set of DFTs (using for example DFT ALUs 261 in FIG. 6) to generate code spectrum data which can be stored in a code spectrum array (such as the code spectrum memory 263 shown in FIG. 6). In one embodiment, operation 205 can be performed by the code generator 259 which generates the code array data that can then be processed by the DFT ALUs 261 shown in FIG. 6 to generate the code spectrum array (in column order) stored temporarily in the code spectrum memory 263.

It should be noted that the code Doppler on E5-band signals is much faster than the code Doppler in the L1 band. This code Doppler is the carrier Doppler scaled by the ratio of the carrier cycles to code chips. At L1, there are 1540 carrier cycles per code chip. At L5 for example, there are 116 carrier cycles per code chip. Thus, the number of code chips at L5 is 13.28 times faster, meaning that the correlation in the E5-band requires a faster update of the code phase to accommodate consistent correlation over consecutive frames of the PRN codes. This means it is not normally possible to pre calculate this effect. An alternative solution is apply the code Doppler effect on the correlation results prior to adding to the hypothesis memory. The storage address can be shifted to account for the code Doppler, but this leads to some loss as the shift is quantized to the number of hypotheses, usually around 2 hypotheses per code chip. Thus, applying the code Doppler to the generated codes prior to generating the code spectrum is preferable. Another optimization is to up-multiply the carrier Doppler onto the generated codes to match the carrier information in the input samples. In this way, the DFT of the input samples need only be performed once per millisecond, for each sideband and or center band, and the same input spectrum can be used for all the correlations in that millisecond.

In operation 207 a set of DFT ALUs, such as the DFT ALUs 255 shown in FIG. 6, can perform concurrently multiple DFTs, using a decimation in time method, on the loaded GNSS baseband data and store the results in a frequency domain result memory, such as the memory 257 shown in FIG. 6. In the example shown in FIG. 6, operation 207 performed by the DFT ALUs 255 results in an array which is arranged in a column order stored in the memory 257, and the data in this memory 257 can be retrieved to provide an output 258 shown in FIG. 6. The output 258 in operation 209 can be multiplied by the code spectrum stored in the code spectrum memory such as the code spectrum memory 263; in the example shown in FIG. 6, the multiplier 265 performs this multiplication of operation 209 and produces a product array of data. Then in operation 211 a set of inverse DFTs can be performed using a decimation in frequency method on the data in the product array, and these DFTs can use conjugated inputs to produce the inverse DFTs. In one embodiment, the inverse DFT ALUs 267 shown in FIG. 6 can perform operation 211, and the output from the inverse DFT ALUs 267 can be processed in a correlation post processing operator 269 shown in FIG. 6 and then stored in operation 213 in a memory which can be referred to as an integration memory (such as memory 271 shown in FIG. 6) which in one embodiment can store hypothesis data during the acquisition phase. In one embodiment, this integration memory can be in a portion of cache memory (e.g., cache memory 70) allocated for use by the acquisition engine of the GNSS processing system that includes the array correlator in FIG. 6. The GNSS processing system can then perform operation 215 by determining frequencies of acquired PRN codes which identify the GNSS SVs that have transmitted the acquired PRN codes. Once it is confirmed that GNSS signals have been acquired from a particular GNSS SV then operation 217 can be performed for each GNSS SV's signals that has been acquired by entering the tracking mode for those acquired GNSS signals. In one embodiment, tracking mode can use conventional correlators or other techniques such as DFTs to determine pseudoranges to acquired and tracked GNSS SVs. This is shown as operation 219 in FIG. 5B. The GNSS processing system can then use the determined pseudoranges to derive a location of the GNSS receiver by using the pseudoranges with ephemeris data to the tracked GNSS SVs to derive the location (e.g., a latitude and a longitude of the GNSS receiver) as is known in the art.

FIG. 6 shows an example of a fast frequency domain correlator architecture which can perform the method shown in FIGS. 5A and 5B. The memory 253 can be a circular buffer memory which stores N2 by N1 samples of digitized GNSS signals. In one embodiment, memory 253 can be two circular memory buffers storing 1.05 or 1.25 ms of GNSS sample data; one of these circular memory buffers can store the GNSS sideband A sample data and the other can store the GNSS sideband B sample data. The two different sidebands can be separated and then store using the following method. To get the upper sideband (e.g. E5B or B2B), the GNSS sample data is digitally carrier shifted down (for the sampler centered at 1191.795 MHz) by for example 15.345 MHz (and hence will now represent information in the sample data originally at 1207.14 MHz) and then the shifted sample data is filtered by a low pass filter to capture+/−10.23 MHz of bandwidth of data and then the filtered sample data is decimated from a wideband sample to a lower sample rate for processing in the pipeline shown in FIG. 6. To get the lower sideband (e.g., E5A or B2A or L5 or QZSS), the GNSS sample data is digitally carrier shifted up (for the samples centered at 1191.795 MHz) by for example 15.345 MHz (and hence will now represent information in the sample data originally at 1176.45 MHz) and then the shifted data is filtered by a low pass filter (LPF) to capture+/−10.23 Hz of bandwidth of data and then the filtered data is decimated from a wideband sample to a lower sample rate for processing in the pipeline shown in FIG. 6. The DFT ALUs 255 retrieve data from the memory 253 and perform a set of DFTs in the DFT ALUs 255; FIG. 7 shows an example of the components within the DFT ALUs 255. In the example shown in FIG. 7, there are two stages of DFTs. The first stage uses N1 DTFs, each of which operates on 1024 points based upon inputs which include a phase factor inputs from the array 301 and the input of the data from the memory 253 which can be similar to the data shown in the array 157 in FIG. 4. The input to this array is the input 251 which can be provided by, for example, an analog-to-digital converter such as the RF ADC 155 shown in FIG. 4. FIG. 7 shows a set of 20 DFT operations three of which are shown as operations 303, 304, and 306. The result of these operations can be stored in a partial result sample array 308 which in turn provides an output that is used as an input to the second stage in which there are N2 DFTs; these N2 DFT operations include the two operations 313 and 315 shown in FIG. 7. One of the inputs to these N2 DFTs is a set of phase factors from an array 311. The output from these DFTs operations in the second stage shown in FIG. 7 is stored in an FFT result array 257, and the data is stored in a column order which is reversed from the row order in which the data is stored in the memory 253. This reversal allows for the data to be prepared for the inverse DFTs operations, such as those operations performed by the inverse DFT ALUs 267 without having to transpose or otherwise reformat the data.

FIG. 8 shows an embodiment of the inverse DFT ALUs 267. In the example shown in FIG. 8, the inverse DFT ALUs can include two stages of DFT operations that receive data from the product array from the multiplier 265. The first stage can include N2 DFT operations which use data from the product array generated by multiplier 265 (with conjugated inputs) and also use phase factors from a phase factor array 351 to generate outputs which can be stored in a first stage sample array 361. Each of the N2 DFT operations in FIG. 8 is performed on 20 points of data. FIG. 8 shows two of the DFT operations 355 and 357 of the total of N2 DFT operations. The second stage of DFT operations uses, in the example shown in FIG. 8, N1 DFT operations each of which operates on N2 points; FIG. 8 shows three of these operations 363, 365, and 367, each of which receive a column of data from the first stage sample array 361. These DFT operations in the second stage also receive a phase factor input from the phase factor array 353, and these DFT operations in the second stage produce 20 outputs that can be post processed in post processor 371 shown in FIG. 8. The result of the post processing can be stored in the integration array 373 which can be the same as the integration memory 271 shown in FIG. 6. The phase factors from arrays 301 and 311 (in FIG. 7) and arrays 351 and 353 (in FIG. 8) specify the amount of phase shift required for each radix—20/16/8 DFT on each stage of the FFT. These phase shift amounts are used for the decomposition, in one embodiment, of a 20480 point DFT into multiple stages of radix—20/16/8 DFTs, which is the basis of an FFT implementation of a DFT. The phase factors are also referred to as “twiddle factors” of an FFT.

FIGS. 9A, 9B, 9C, and 9D show an example of a spectrum code generator (and portions thereof) which can generate the spectrum code which is stored in code spectrum memory, such as code spectrum memory 263 in FIGS. 6 and 8. In one embodiment, the code generator 259 and the DFT ALUs 261 shown in FIG. 9D can generate PRN codes and/or their code spectrum from DFTs for only the GNSS SVs that are in view on demand and on the fly while the GNSS processing system is acquiring and tracking these GNSS SVs without storing (beyond momentary storage for a few clock cycles in registers and buffers in the processing pipeline) the generated PRN codes and/or their code spectrum from DFTs; this can improve memory usage by the GNSS processing system by reducing the amount of memory required to operate the GNSS processing system. In an alternative embodiment, the spectrum code generator can generate the PRN codes and/or their code spectrum from DFTs for only the GNSS SVs that are in view on demand but store those codes during the acquisition and tracking phases until one or more locations, such as one or more latitude and longitude values, are determined. Thereafter, the PRN codes and/or their code spectrum from DFTs can be deleted from storage to allow other uses of the storage. In one embodiment, as shown in FIG. 9D the code spectrum generator 259 can use a polynomial type generator 402 (shown in FIG. 9A) to generate the PRN codes from a code seed 401 for each GNSS SV that is in view. Then a set of programmable coefficients can be used to time shift the generated PRN codes in the time shifter 404 (based upon those coefficients) and then the generated and time shifted PRN codes can then be frequency shifted by a frequency shifter that can use CORDIC phase rotations, 3 of which are shown as CORDIC phase rotation 408, 410, and 412. The phase rotations can be based on a programmable phase split input 406. Then a further set of CORDIC phase rotations, including phase rotations 417, 419, and 421, can produce an output that is then processed with DFT operations (performed by DFT ALUs 261 in FIG. 6 in one embodiment) that are the same as the DFT operations performed on the digitized GNSS sample data. The result of the DFT operations (performed by DFT ALUs 261 in FIG. 6 in one embodiment) is then stored in one embodiment in the code spectrum memory, such as code spectrum memory 263 shown in FIG. 6.

One embodiment of the polynomial type generator 402 is shown in FIG. 9A. This embodiment can be used to perform the method shown in FIGS. 9B and 9C. This generator 402 includes two computed (or precomputed) code advance matrices 501 and 502 retrieved, for example, from a lookup table if precomputed. For example, for each of the four components of the Galileo E5A and E5B signals, there is a corresponding code seed and primary code polynomial data; this information is well known in the art and published in the ICD of the source of the GNSS's constellation. The generator 402 can generate more than 2 bits of primary PRN code bits in a single clock cycle by using the computed code advance matrices 501 and 502; see operations 955 and 957 in FIG. 9B. As shown in FIG. 9A, the computed code advance matrix 501 includes a first input to receive generator polynomials 503, which can be the primary code polynomial data for a given GNSS constellation and a given GNSS signal component, and includes a second input to receive a value fed back from register 515 and includes an output that is a first input to multiplexer (MUX) 511. A second input 507 to the MUX 511 is a constant initial value of all 1's (14 bits, each set to the value of 1 in one embodiment); this second input 507 is used only on the initial output from register 515, and thereafter the MUX 511 selects the first input (to MUX 511) as the output from the MUX 511, and that output is stored in register 515 (which can be a clocked register) so that on the next clock cycle, the last output from the MUX 511 is fed back to the second input of the code advance matrix 501 and is also provided as a first input to XOR logic gate 519. The output from MUX 511 that is fed back to the second input (of code advance matrix 501) is multiplied by the constant values (derived from the generator polynomials 503) in the code advance matrix 501 to generate the next output from the code advance matrix 501, and that next output passes through MUX 511 and is stored in register 515; this process of feeding back the output from register 515 and performing a matrix multiplication of that output and the constant values in the code advance matrix 501 is repeated on each clock cycle (or alternatively in a set of a few clock cycles) to generate N bits of primary PRN codes, in each clock cycle, for the given GNSS constellation (e.g. Galileo E5) and the given GNSS signal component (e.g. ESAI). In one embodiment, N can be greater than 2, such 10 or 14 bits. Thus, the generator 402 can rapidly generate many (e.g. N) bits of primary GNSS PRN codes in one clock cycle or a few clock cycles. In the example shown in FIG. 9A, 14 bits are generated at the output from register 515, but only the last 10 bits are used by XOR logic gate 519 (which performs an exclusive OR logic operation). The code advance matrix 502 is used in a manner that is similar to the use of code advance matrix 501. The code advance matrix 501 and the code advance matrix 502 are (in one embodiment) precomputed to, for a given GNSS constellation and GNSS signal component and a given seed for a GNSS SV in the given constellation, generate (at the output of XOR logic gate 519) the next N bits (an “advance” of N bits) of the primary GNSS PRN code for that GNSS signal component from that GNSS SV based upon the values in the matrix and the prior output from the registers 515 and 517. The Matlab appendix includes an example, in the well known form of Matlab code, of a code generator 402 that can create and use these precomputed code advance matrices. In one embodiment, the precomputed code advance matrices can be precomputed (or computed at run time) by multiplying an original matrix containing the primary polynomial data N times to provide N bits of advance in the PRN code for each clock cycle. For example, if an advance of N=3 is desired, then the original matrix (“A”) is multiplied 3 times (A*A*A) to provide a code advance matrix for N=3 bits of output of the next 3 bits in the PRN code. As shown in FIG. 9A, the computed code advance matrix 502 includes a first input to receive generator polynomials 505, which can be primary code polynomial data for a given GNSS constellation and a given GNSS signal component, and includes a second input to receive a value fed back from register 517 and includes an output that is a first input to the MUX 513. A second input 509 to the MUX 513 is a seed value for a corresponding GNSS SV in the given GNSS constellation. This seed value is used only on the initial output from multiplexer 513 and from the register 517 and thereafter MUX 513 selects the first input (to MUX 513) as the output of the MUX 513, and that output is stored in register 517 (which can be a clocked register) so that on the next clock cycle, the last output from MUX 513 is fed back to the second input of code advance matrix 502 and is also provided as a second input to the XOR logic gate 519. The output from MUX 513 that is fed back to the second input (of code advance matrix 502) is multiplied (in a matrix multiplication operation) by the precomputed values in the code advance matrix 502 to generate the next output from that code advance matrix 502, and that next output passes through MUX 513 and is stored in register 517. The outputs from registers 515 and 517, on each clock cycle, are exclusively OR'd by XOR logic gate 519 to give 10 new bits (i.e. 10 bit advance of the PRN code); the 14 bit output is truncated to give the 10 new bits in the current clock cycle. Code advance tens 524 can select the truncation. Then, XOR logic gate 521 performs an exclusive OR operation on the output from XOR logic gate 519 and the secondary code bit 523 of the given GNSS signal component from a given GNSS SV to “wipe” or “remove” the secondary code from the code generated at the output of XOR logic gate 519. The shift left logic 527, the up sample logic block 529 and the shift left logic 533, along with registers 526 and 531, further process the generated primary PRN code to provide code samples that can be “aligned” with received GNSS samples at a particular sample rate so that the sample rates match and can be aligned. The shift logic can be used to shift or move to different parts of the PRN code. The output from shift left logic 533 is provided to time shifter 404 in the code spectrum processing pipeline shown in FIG. 9D.

FIGS. 9B and 9C show a method for operating the code generator 402. In operation 951, a GNSS processing system determines the GNSS SVs in view from, for example, conventional assistance data such as a recently downloaded version of a GNSS satellite almanac or from ephemeris data in the form of equations. In one embodiment, the GNSS SVs in view can be limited to only L5 WB GNSS SVs such as one or more of the Galileo E5 GNSS constellation, the US L5 GNSS constellation, and the Chinese Beidou/Compass B2 constellation. Then in operation 953, the GNSS processing system can determine, for each GNSS signal component from a GNSS SV in view (e.g., E5AI and E5BI of a Galileo E5 GNSS SV) a code seed and a code generator polynomial which can be a set of known coefficients for that signal component in order to generate a primary PRN code for that GNSS signal component. Then in operation 955, a G1 code advance matrix is computed (or was precomputed and is retrieved from a lookup table in non-volatile memory), and in operation 957, a G2 code advance matrix is computed (or was precomputed and is retrieved from a lookup table in non-volatile memory). In one embodiment, each of the G1 and G2 code advance matrices are precomputed by multiplying an original matrix of primary code polynomial data N times, where N represents a desired number of code bits to generate. For example, if the amount of code “advance” is 10 bits of primary PRN code data then the original matrix is multiplied (by itself) ten times to create a 10 bit code advance matrix. The amount of code “advance” is the number of bits, in one embodiment, of primary PRN code data that is generated in one clock cycle, so if N=10, then the code generator generates 10 new bits of the primary PRN code data for each clock cycle. After the G1 and G2 code advance matrices are retrieved (if precomputed) or computed, then the method can continue in operation 959. In operation 959, the system uses the initial vector (all 1's) to provide the first G1 output (so the first G1 output is the initial vector of all 1's) and the system uses the code seed to provide the first G2 output (so the first G2 output is the code seed); in operation 961, the system performs an exclusive OR operation on the first G1 output and the first G2 output to provide the first set of N-bit PRN code data. After operation 961, the first set of N-bit PRN code data is processed in operations 969, 971, and 973 (as processing proceeds via 9X from operation 961 to operation 969 as shown in FIGS. 9B and 9C) and all subsequent sets of N-bit PRN code advances are generated in the loop of operations 963, 965, 967, 969, 971, 973 and 975. In operation 963, the G1 output (e.g. from register 515 in FIG. 9A) is fed back to the G1 code advance matrix and the G2 output (e.g. from register 517 in FIG. 9A) is fed back to the G2 code advance matrix. Then in operation 965, the last G1 output (e.g. from register 515) and the G1 code advance matrix are multiplied to generate the next G1 output and the last G2 output (e.g. from register 517) and the G2 code advance matrix are multiplied to generate the next G2 output. In operation 967, the G1 and G2 outputs are exclusively OR'd (e.g. in XOR logic gate 519 in FIG. 9A). In operation 969, the code output from XOR logic gate 519 is exclusively OR'd (e.g. in XOR logic gate 521) with the expected secondary code bit (e.g. secondary code bit 523) in order to wipe or remove the secondary code from the code output. Then in operations 971 and 973 code samples are generated and provided to the remainder code spectrum processing pipeline. These operations prepare the code samples so that their sample rate can match the sample rate of received GNSS sample data. Operation 975 determines whether to continue generating the GNSS primary PRN code data. In one embodiment, when tracking of all needed GNSS signals is completed, then generation of PRN code data can be terminated, but if such tracking is needed then the process continues in the loop of operations 963-975.

FIG. 10 shows an example of a GNSS processing system which can be used to perform the methods described herein or which can be used implement the systems described herein. The GNSS processing system 450 can be implemented on its own integrated circuit such as a navigation chip 451 or be part of a system on a chip architecture that is part of a larger system such as a smartphone or tablet computer etc. The GNSS processing system 450 can include processing logic such as an ARM processor 466 which uses ARM program and data memory 467 to control the operations of the GNSS processing system 450. Further, the GNSS processing system 450 can include an RF ADC 465 that can be similar to the RF ADC 155 shown in FIG. 4. The GNSS processing system 450 can also include clock phase locked loop generation and gating circuitry 464 to generate clocks using phase lock loops and for other operations in the GNSS processing system 450. The GNSS processing system 450 can include both logic modules and memory in order to perform the acquisition and tracking processes described herein. For example, logic module 457 can include an acquisition engine 458 which can include a set of DFT and inverse DFT processors or ALUs to perform the DFT operations described herein. In addition, the logic module 457 can include a digital front end 460 which can be in all digital E5 GNSS front-end providing processing both before and after the RF ADC 465. The logic module 457 can also include a plurality of satellite signal generators such as the satellite signal generator 459 which generates GNSS PRN codes for GNSS satellites (SVs) in view based upon assistance data that can be received, for example, from a cellular data communication network. The logic module 457 can also include a timebase and control module 461 and a memory interface and bus control module 462 to allow the GNSS processing system to couple to one or more application processors. The logic module 457 can be coupled to one or more memories to store various data in various data structures including, for example the baseband sample memory 468, the acquisition engine command memory 469, the FFT program memory 470, the FFT constant memory 471, the FFT variable memory 472, the FFT result memory 473, code spectrum generation memory 474, the coherent integration memory 475, the IFFT memory 476, the IFFT memory 477, the IFFT variable memories 478, and the non-coherent integration memory 479. These memories can be used with the logic module 457 to perform the operations described herein. It will be appreciated that alternative architectures may use different processors and memory arrangements than shown in FIG. 10.

In another embodiment, the clocks required to perform the DFT operation is reduced by performing multiple kernel operations in parallel. For example if the sample rate is chosen to be 2{circumflex over ( )}N, for example, N=14, then the DFT can be implemented with a radix 4 kernal that has 7 stages. 4 samples are processed in place each step of each stage. Assuming only dual port memory, with one read and write per cycles, the clocks required is 4*4096 per stage and with 7 stages is 114,688 clocks. The VFFDC shown in FIG. 6 can achieve a DFT in around 4096 clocks. To achieve similar performance, 32 kernals could be implemented in parallel so that a stage could complete in 512 clocks, and 7 stages would be complete after 3584 clocks. However, this approach would require the ability to reach 32 input sample in a parallel. Thus, the advantage of the VFFDC is that it can achieve a low clock rate with only reading 10 memories in parallel. Another embodiment is to use a four times higher clock rate, and then only require 8 kernals in parallel, which reduces the parallel memory reading requirement to 8 inputs/outputs per clock. The advantage of the VFFDC is that is maintains both a low clock rate and low parallel memory read/write configuration. Such an optimization should allow low power consumption as the system can operate at a low clock speed and enable reliable timing at low voltage.

The VFFDC implements in one embodiment a processing chain that has the lowest memory requirements. Each millisecond, there are two DFTs on the input sample, one for each of the upper and lower sidebands of E5. Then for each component of each satellite signal (4 for E5, 2 for L5, and 4 for the future B2), there is one DFT that includes the effect of the code Doppler and carrier frequency, so that it is not necessary to apply a different DFT on the input samples to remove the carrier frequency hypothesis. Then there is another DFT to implement the inverse DFT of the products of the input and code spectrums. Thus, the total number of DFTs per millisecond is 2+2*N channels*M components where the first 2 is the original input DFTs and the second 2 is to make the code spectrum and IDFT of the spectrum products. For 22 channels with up to 4 components per channel, this is 2+2*(22*4)=178 DFTs per millisecond. In case the code spectrum DFTs are precomputed, then the input samples must be unique for each frequency of each PRN. In that case, the number of DFTs is (2*M*N)=176 for M=4 and N=22. However, this requires a memory to store the code spectrums. Such a system will also need a method to generate the code Doppler after each IFFT and before updating the hypothesis memory. Thus, even though the alternative is nearly the same number of DFTS, it requires additional memory and could have higher power consumption to move the code spectrum DFTs into the AE every msec. For example, at 20480 hypotheses per msec, it would require a bus rate of 22 channels*4 components*2 bytes for I,Q of code spectrum*20480 hypotheses*8 bits per byte 28 Mbit per msec=28 Gbit per second. Such a configuration would be nearly impossible to implement. Thus, the compute in place capability make the system realizable.

Another optimization to reduce system memory is to allow all four components of the E5-band signals like Galileo E5, and the future B2 to be processed into a single hypothesis memory for long integration to overcome weak signals due to either high system loss in cell phones and or high loss due to foliage or user body attenuation of the signal. The public domain interface control documents for B2 only describe the lower sideband, but other technical papers suggest that the upper sideband signal structure will be available late 2019 or after. Thus, GPS L5 with only one sideband will have only two components whereas E5 and B2 will have 4 components: two on each of an upper and lower sideband.

The primary challenge in coherently integrating the sum of each millisecond code correlation is in reducing cancellation losses due to the phase reversals at the 1 ms epoch. In cases where the received signal primary code phase can be estimated to on the order of 0.5 ms or less, it is possible to at least partially align the received signal spectrum in time with the estimated code phase, such that sub-millisecond cancellations are avoided. FIG. 11 shows an embodiment that can provide precise time coherent integration.

Estimating expected fractional primary (ms-long) code phase for candidate signals requires, in one embodiment, knowledge of both precise time and initial position. Precise time may be derived from the secondary code phase of a first received signal or it may be derived from a source of fine time, which is already well known in the art. This estimation can be operation 601 in FIG. 11.

Once primary code phase uncertainty is reduced to well under 1 ms, the sub-millisecond cancellation problem can be resolved by at least partially aligning the received 1 ms signal epoch with the time the code from each SV is expected to be received. This means that a plurality of received signal spectrums must be computed every millisecond, staggered in time to match the primary code spectrums and thus reducing the level of sub-ms coherent cancellation.

The search order can establish which SVs, their signal components and Doppler bins will be searched at each fractional phase offset. This is shown as operation 603 in FIG. 11. Because long coherent integration produces greater sensitivity, the E5Aq and E5Bq pilot signals may be preferentially used, due to their 100 ms long secondary codes and no data bit reversals. In one embodiment, E5Ai and E5Bi may also be used in cases where the navigation message symbols are predicted and removed, thus eliminating or reducing their respective coherent cancellation losses. It should be noted that while the primary code phases of all signals are expected to be uniformly distributed across the millisecond, there will likely be cases where the only processing slot available for a given signal is sub-optimal. Regardless, it will always be possible to avoid the worst-case, where the first ½ ms of signal would cancel the second in cases of a secondary code bit reversal.

In one embodiment of the present invention, M 1 ms signal spectrums would be computed per millisecond, each offset by 1/M ms. For example, if M=4, then every 0.25 ms, a full 1 ms (or more) of received and digitized GNSS sample data would be processed by FFT correlations (e.g. using the VFFDC architecture shown in FIG. 6), so in this case the processing epochs are separated by and offset (one to the next) by 0.25 ms and the received GNSS sample data is also offset by 0.25 ms. In this example a first processing epoch at relative time 0.0 ms would process FFT correlations on 1 ms of GNSS sample data generated in operation 605. The correlations are shown as operation 607 in FIG. 11. A second processing epoch at relative time 0.25 ms would process FFT correlation (operation 607) using 1 ms of GNSS sample data that ends at the relative time 0.25 (operation 605) and is offset from the prior 1 ms of GNSS sample data by 0.25 ms. A third processing epoch at relative time 0.5 ms would process FFT correlations (607) using 1 ms of GNSS sample data that ends at the relative time 0.5 ms (operation 605) and is offset from the prior 1 ms by 0.25 ms. Thus operations 605, 607 and 609 are repeated four times during a 1 ms time interval. In an alternative, more sensitive, embodiment, the signal spectrums would be computed to align as closely as possible with each expected satellite code phase.

As in the case of coarse-time mode, candidate signal codes (received GNSS sample data) and their associated spectra must be generated and aligned each millisecond and correlated with signal spectra using VFFDC, or similar FFT-based.

As these resultant correlations are produced they must be summed, with the phase reversals associated with the secondary code removed, in coherent hypothesis memory specific to each SV frequency band and frequency bin. This is shown as operation 607. This process requires that the full 1 ms correlation be computed, even though there is much less than 1 ms of code phase uncertainty. However, only that fraction of the full PN code that is likely to contain a correlation peak must be stored in hypothesis memory.

At secondary code epoch boundaries, or in some cases even more often, the coherent hypothesis memory must be summed non-coherently into non-coherent hypothesis memory, which mirrors the coherent hypothesis memory but contains only magnitude information and can therefore be kept in half as much memory. This is shown as operation 611.

The process in FIG. 11 continues in operation 613 (by looping back to operation 605) until a correlation peak rises above the noise floor. Once the correlation peak rises above the noise floor with sufficient confidence, the search results are reported and the acquisition search for the particular SV of interest may be discontinued, making way for the next SV in the search order for its fractional code phase. The search may also time out after a preset time interval and a search failure may be reported.

FIG. 11 shows an example of a method about how satellite codes can be searched in alignment with the approximate time bin in which they are expected to be received such that submillisecond coherent cancellation losses due to phase reversals can be reduced. This search can be performed based upon an initial set of information that can include, in one embodiment at least two of: (1) a code phase of a received primary or secondary code signal from at least one GNSS SV; (2) an estimated GNSS time based on one or more sources of time, the estimated GNSS time uncertainty being estimated (e.g., based on the known accuracy of the source) or known to be within less than +/−0.5 milliseconds of actual GNSS time; and (3) an approximate location of the GNSS receiver. Using this initial set, operation 601 in FIG. 11 can be performed. In effect, this initial set gives the system an estimate of GNSS time to enable acquisition using GNSS time.

Another aspect of this disclosure involves the use of only a subset of the two or four components of the GNSS signals (a selected component) to first acquire that subset (such as only one of the four components) during coarse time acquisition and then acquire the remaining components. In one embodiment, this selected component is selected based on a lowest probability of signal change due to sign or phase reversals due to the coding scheme used in that selected component. In the case of Galileo's E5 GNSS signals, the E5BI component has the lowest probability of signal change due to sign or phase reversals (see the appendix for a detailed explanation of various probabilities for different signal components) and thus can be used as the selected component to perform a coarse or precise time acquisition before attempting to acquire and/or track the remaining components in the Galileo GNSS signals. FIG. 13 shows an embodiment of a method that uses this aspect which uses only a subset of components. The method can begin in operation 801 shown in FIG. 13; in operation 801 a GNSS processing system in a GNSS receiver receives a request, such as a request from an application processing system, for position information. In operation 803, the GNSS processing system determines a need or desire to switch to a reduced acquisition mode; this need or desire may result from a failure of a conventional acquisition which attempted to acquire a full set of GNSS signal components from a set of GNSS SVs in view of the GNSS receiver. For example, the GNSS may fail, within a predetermined period of time, to acquire the E5AI and E5AQ signal components from several SVs in the Galileo constellation. This failure can trigger the GNSS processing system to switch to a reduced acquisition mode in which it will attempt to acquire, in an initial acquisition phase, only the selected component from each SV in a set of SVs in view. In operation 805, the GNSS processing system attempts to acquire only the selected component; in one embodiment, this is the E5BI signal component, and the GNSS processing system can attempt to acquire this signal component from several GNSS SVs. If, in operation 807, the GNSS processing determines that the selected component has not yet been acquired, then the processing system can revert back to operation 805 to continue to attempt to acquire the selected component. If, in operation 807, the GNSS processing determines that the selected component(s) have been acquired, then the GNSS processing system can proceed to operation 809 to acquire other components from the same SVs; for example, the GNSS processing system in operation 809 can attempt to acquire the other signal components, such as E5BQ, E5AI, and E5AQ from the same SVs. In operation 809, the GNSS processing system can use time and phase information acquired from the acquisition of the selected component from each SV to facilitate the acquisition of the other signal components. The method shown in FIG. 13 can also be used as a method to acquire a stronger satellite more quickly as the number of correlations is reduced, allowing a portion of a GNSS acquisition engine to search a large frequency space for many SVs more quickly and with lower power than if more GNSS signal components are employed.

Modernized GNSS signals in the L5 frequency band are susceptible to interference from aeronautical radio navigation (ARN) signals that are often near, for example, airports or military bases. This interference can be mitigated using one or more embodiments described herein, such as the embodiments illustrated in FIGS. 15A and 15 B.

In the embodiment shown in FIG. 15A, a GNSS receiver can receive, in operation 821, both GNSS signals in the L5 frequency band and ARN signals. Generally, the GNSS receiver can include hardware that can measure signal levels, such as signal strength levels, and these measured signal levels can be compared, in operation 825, to a predetermined noise floor. This predetermined noise floor can be fixed over time or dynamically adjusted over time, but in most instances, the GNSS signals from GNSS SVs will be below the noise floor. The noise floor can be set based on known signals strengths of GNSS signal relative to known signal strengths of ARN signals. ARN signals will, when the GNSS receiver is near a source of ARN signals (e.g., the receiver is near an airport), generally be above the noise floor. Thus, operation 825 can be used detect the presence of ARN signals by comparing the received signals to the noise floor. In one embodiment, a predetermined threshold above the noise floor can be used so that the ARN signals must exceed the predetermined threshold (that is above the noise floor) before operation 829 is used to remove ARN signals. In one embodiment, the ARN signals can be detected during the signal acquisition phase using the DFT array processing techniques described herein; in this embodiment, operation 829 can be invoked when the ARN signals are detected in the frequency domain. When the ARN signals are detected above the noise floor (or the ARN signals are detected in the frequency domain), a GNSS processing system in the GNSS receiver can, in operation 829, remove the ARN signals before correlation processing of the GNSS signals. In one embodiment, the ARN signals can be removed by a finite impulse response filter; the finite impulse response filter can receive the signals containing both GNSS signals and ARN signals and provide a filtered output containing the GNSS signals (with a significantly reduced amount of ARN signals in the output). In another embodiment, a configurable notch filter used in an intermediate frequency (IF) bandpass filtering operation (e.g., in the receiver architectures shown in FIG. 4D, 4F, or 4J) can be used to filter out the ARN signals before GNSS correlation processing.

In the embodiment shown in FIG. 15B, the mitigation of known interfering signals, such as ARN signals, can be achieved by narrowing the bandwidth of the GNSS radio receiver. FIG. 15B shows an example of a method to narrow the bandwidth to one of two sidebands in the GNSS signals. In operation 835, the radio receiver can receive both GNSS signals and ARN signals through one or more antennas. The GNSS signals can include two sidebands such as the E5A sideband and the E5B sideband. In operation 839, the GNSS receiver can detect interference in one of the two sidebands caused by an interfering signal such as the ARN signal. In one embodiment, this detection can be performed by observing the input data spectrums as the spectrums are received and processed every millisecond at each of the upper and lower sidebands. The detection can involve detecting a difference in the level of interference, such that one sideband has little or no interference while the other sideband has considerable interference. In response to this detection, the GNSS processing system in the GNSS receiver can configure, in operation 842, the GNSS processing system to process the sideband having less interference, such as less ARN interference, and not process (e.g., no correlation processing) the sideband having more interference. In this situation, only one sideband is used to derive codephase measurements and to determine location data while the other sideband is not used to determine location of the GNSS receiver. In one embodiment, the GNSS receiver can continue to monitor the interference and switch between using the two sidebands in response to changes in the interference; for example, the GNSS receiver may initially use the lower sideband (such that GNSS signals from the lower sideband are processed while GNSS signals from the higher sideband are not processed to determine location) while the higher sideband experiences greater interference and then switch to the use of the higher sideband when the lower sideband experiences greater interference.

Single Hypothesis Memory

Another aspect of this disclosure involves the use of a single hypothesis memory to accumulate or sum amplitude for codephase hypotheses for multiple signal components from the same GNSS SV, such as a GNSS SV in the Galileo constellation of GNSS satellites. This technique can improve sensitivity by summing for example the codephase hypotheses for the E5BI, E5BQ, E5AI and E5AQ signal components from the same GNSS SV in the Galileo constellation of GNSS satellites. This accumulation can be done non-coherently when the time uncertainty is more than 0.5 millisecond (ms). This accumulation can also reduce the amount of memory used by the GNSS receiver.

Galileo E5 has four components: a data and pilot component on each of the two sidebands. GPS L5 has only two components, a data and pilot component but only one sideband. BDS B2A and B2B also have four components, a data and pilot component on each of the two sidebands. QZSS has two components: a data and pilot component but only one sideband.

In general, each component has its own primary and secondary code. With the multiple components, it is also assumed that the primary codes are the same number of bits and repeats at the same time on all components. It is assumed that the secondary codes can change at the completion of each primary code. The length of the secondary code does not need to the same on each component, and in general each system has different length secondary codes on each component. For modernized signals, the chipping rate is 10230 bits in one millisecond.

In general, the sample clock is chosen to be near twice the chipping rate so as to minimize the worst case loss in the case where the signal arrival time is midpoint between two adjacent samples. A faster sample rate, that is, greater than twice the chipping rate, reduces this loss but increases the number of correlations to be performed, and also increases the size of the integration memory. A slower rate, that is less than twice the chipping rate, increases the loss but also deceases the number of correlations to be performed and also reduced the size of the integration memory. In general, the average loss is considered more important to the worst case loss.

The preferred embodiment has a sample rate near twice the chipping rate, but also has a rate that can be expressed as the product of N1 and N2, where N2 is a large power of 2 so that the FFT can be employed to reduce computation with respect to a DFT. Here the sample rate is chosen to be 20480 samples per msec, so that N1=20 and N2=1024. Another option is N1=5 and N2=4096, as N1=10 and N2=2048.

For two samples per chip, the worst case loss is when the true arrival codephase is midway between two samples. The correlation function is +/−1 chip, and so there is 0.25 chips on either side of the true codephase. In this case, the correlations yield 75% of the correlation, yielding a loss of about 2.5 dB. (0.75=1-0.5/2=1-0.25)

Another embodiment is N1=1 and N2=16384. This arrangement uses the largest possible FFT size but undersamples with respect to the 2 samples per chip approach above. Here there are 10230/16384=0.6244 chips/sample, or 1.6 samples per chip. The worst case correlation is now 69% of the maximum: 0.69=(1-0.624/2), for a worst case loss of 3.25 dB, or an increase in the loss of only 0.75 dB. This configuration reduces the number of correlations by 25% and reduces integration memory by 25%.

Modernized satellite broadcast additional power spread across multiple components. One method to improve sensitivity is to correlate more than one component in parallel from the same input sample data signal and then to sum up all the single component amplitudes or powers at each correlation hypothesis into the signal detection test. The signal information at each codephase hypothesis for all components is compressed by summing into a single value, that is integrated for each codephase hypothesis. At each frequency bin to be searched, the number of codephase hypotheses equals the number of correlations per primary codephase, which is 20480 for a sample clock 20.48 Mhz and 10230 chip primary code in one millisecond.

At each codephase, each primary code sequence is tested at all possibly candidate phases for each component. This is done optimally with the DFT implemented at the N1 and N2 point FFTs; see for example the embodiments shown in FIGS. 6-8. This produces the 20480 amplitudes for each component.

There are two ways to combine: coherently or non-coherently.

The preferred embodiment is to combine non-coherently as in general, the time uncertainty is larger than a 1% millisecond, and thus, it is impossible to predict the secondary code phase. Furthermore, the random data bit phase makes it difficult to predict the phase between the data and pilot channels even if the secondary codephase is known.

The amplitude of the complex correlation at the same codephase hypothesis is computed for each component and is added into a single value, that is integrated into a single memory bin. FIG. 14N shows an example of an arrangement of hypothesis memory with multiple bins; each of these bins can store an accumulated sum of a codephase hypothesis across several signal components. The power could also be computed, but amplitude is preferred as requires fewer bits.

In general, the hypothesis memory is an integration memory. For each primary codephase hypothesis, the new sum of the amplitude for all components from the same GNSS SV for the current millisecond is added to the previous sum in integration memory and this running sum overwrites the previous sum.

Summarizing,

-   -   1) At msec (k), and at each primary codephase hypothesis (j),         form the correlation amplitude of the primary code (i) for each         component:         -   a. AMP(i,j,k)=real(i,j,k)²+imaginary(i,j,k)² for i=1,4 and             j=1,20480, and k=current msec     -   2) Form sum of the amplitude (AMP) at each component for each         codephase         -   a. AMP_ALL(j,k)=sum {AMP(i,j,k)}, for i=1,4 at k-th msec.             That is,             AMP_ALL(j,k)=AMP(1,j,k)+AMP(2,j,k)+AMP(3,j,k)+AMP(4,j,k),             where i=1 is E5A data channel component, i=2 is the E5A             pilot channel component, i=3 is E5B data channel component,             i=4 is the E5B pilot channel component     -   3) Retrieve integration bin for previous msec (k−1) for the         (j-th) codephase hypotheses         -   a. X(j,k−1)=INT_MEM(j,k−1)     -   4) Add in the new amplitude from all 4 components         -   a. X(j,k)=X(j,k−1)+AMP_ALL(j,k)             Store back the updated and current integration sum X(j,k) to             the hypothesis memory for the j-th codephase hypothesis.

In this above method, the number of memory bins is equal to number of codephase hypotheses, which is less than having a similar sized integration memory for each component.

The signal detection then uses the single integration memory so that there is not an individual signal detection on each component. The test is generally:

Obtain the maximum integration memory value from the integration memory across the 20480 hypotheses and remember its memory index X that corresponds to a specific phase, where each bin holds the running sum of the amplitude of all primary code components at that codephase.

Estimate the noise floor mean and standard deviation from the 20480−Y hypotheses, where Y are the integration memory values adjacent to the maximum value at codephase X. Here Y=7 which includes is the maximum at X, and the 3 integration memory sample before and after. In this way, a total of 7 removed samples are ignored so that the noise floor statistics are not affected by the peak hypothesis.

Test that Signal to noise ratio estimate is above a threshold to set the false alarm rate.

Test:

If SNR=10*log 10((X²−noiseFloor²)/noiseVariance)>K, a predetermined threshold to set the false alarm rate acceptably small, then declare signal found and the integration is stopped. Else, declare signal not found and the integration continues.

It should be noted that the carrier frequency produces a code Doppler according the to the well-known relationship between the number of carrier cycles in one chip of the primary code sequency. For E5a at 1176.45 Mhz, there are exactly 116 carrier cycles for each chip. The phase also has a negative rate. Thus, the long integration requires shifting the locally generated code at the rate of the carrier frequency hypothesis divided by −116 chips per second so that the code is maintained to correspond to the initial codephase hypothesis at the start of the integration.

Coherent integration of multiple components into a single hypothesis memory is also possible in case the secondary code phase is known and the data bit phase is known. This is true when fine time assistance is available, and the data bit stream is observed from a second receiver and communicated promptly. This is only possible when the data is repeated or when the known data is made available, which is possible with a communication like the internet.

In addition to the phase reversals from the secondary code sequence and data sequence, signals in the same sideband have a different but known phase offset of 90 degrees between the data and pilot channels. Signals in different sidebands have a different phase offset due to the different carrier frequencies. The frequency offsets of each sideband from the center channel are known however, as the Doppler offsets have the same magnitude but different sign with respect to the center frequency. For example, if the E5 frequency Doppler is 1000 Hz, the E5A Doppler is 992 Hz and the E5B doppler is 1008 Hz. The carrier phase difference rotates with opposite sign, but of equal magnitude between the A and B sidebands. The known phase offsets are applied to the complex correlations by multiplying by the complex exponential with the known phase. In this way, the real and complex components of all adjusted components can be added into a single complex correlation value. The amplitude or power is then integrated into a single hypothesis memory bin for each codephase hypothesis.

Frequency Domain Doppler Compensation

GNSS (Global Navigation Satellite System) signals typically incorporate pseudorandomly modulated (PRN) waveforms in order to achieve precise time of arrival measurement at receiving terminals. Normally a PRN waveform incorporates a repeated code whose duration is called the frame length. Received waveforms are processed using signal processing structures such as a bank of correlators, matched filters, and the like. This invention focuses on GNSS signal acquisition based upon use of fast Fourier transform (FFT) methods that effectively implement a matched filter corresponding to a received signal. This method is particularly attractive when the spreading ratio (SR) of the PRN waveforms is large, that is, the ratio of the signal bandwidth to the frame length is large. In many modern GNSS systems this spreading ratio may exceed 10,000. The FFT is a very efficient algorithm for computing a discrete Fourier transform (DFT) and even though we use the terminology “FFT” throughout we mean by FFT any method for computing a DFT including a large variety of FFT algorithms, including Cooley-Tukey algorithms, prime factor algorithms, chirp z-transform algorithms, etc.

Acquiring a GNSS signal with high SR is made difficult since the time of arrival of the signal must be tested over a large set of time instants (e.g. over 10,000 in the above example) and, moreover, over a large set of potential frequency offsets from a nominal hypothesized carrier frequency, the latter due to Doppler effects and local clock errors. In addition, tests must be done over the set of possible satellite signals present. These sets of time instants, frequency offsets, and satellite signals numbers are termed “hypotheses.” As can be seen from the above, the acquisition of GNSS signals requires search over a large three-dimensional space of hypotheses. The use of FFT methods is very efficient for performing the time hypothesis search since it may process in parallel each possible time hypothesis over the frame length. The FFT approach performs a matched filter operation on a set of incoming time samples by (1) performing a forward FFT on a set of incoming time samples to produce a set of “signal frequency samples”, (2) multiplying the signal frequency samples by frequency samples of a PRN reference signal (termed “reference frequency samples”), and (3) performing an inverse FFT on the result. The set of output samples is then either further accumulated with prior sets of outputs to perform “coherent processing” or the output samples are detected (typically via magnitude or magnitude-squared operations) and accumulated with similarly processed prior sets of data. Such accumulated sets of processed data are observed for the occurrence of large peaks above background noise samples, wherein the location of such peaks are indicative of the time-of arrival of the incoming signal.

As indicated above, in the acquisition process the incoming signal may have associated with it a carrier frequency offset, which must also be determined. Traditional methods for such determination involve hypothesizing a Doppler frequency, compensating the Doppler in the time domain by multiplying the set of incoming samples by a complex sinusoid with a hypothesized frequency to remove the Doppler component and then proceeding with the three steps as above. This process is done for each of a set of hypothesized Doppler frequencies. The problem with this approach with FFT implementation is that it requires one forward and one inverse FFT for each Doppler hypothesized frequency. In many cases one must search over a set of such hypothesized frequencies that is 20 or larger. These embodiments of the invention reduce the number of such FFTs to a number that is approximately half or less than that required in the above prior art approach, thus reducing overall processing time by a factor of approximately one-half or less.

In the following discussion we refer to frequency uncertainties as “Doppler” but the frequency uncertainty can also be due to local oscillator frequency errors. For simplicity of discussion we refer to either frequency uncertainty as “Dopplers” but when doing so we actually mean any source of frequency uncertainty, including perhaps errors on the part of a GNSS transmitter. Also, in the following initial discussion, for simplicity, we ignore the multiplication of the forward FFT data by the reference frequency samples (as discussed above). This is done just before performing the inverse FFT operation in the first example of the following discussion.

It may be helpful to refer to FIG. 16A in the following discussion. Following a forward FFT (1101) considering the FFT output as a vector, if one rotates the vector by m positions (1102) then this is equivalent to a frequency shift equal to the m×bin spacing, where the bin spacing equals the sample rate divided by the number of samples per FFT. Here m is an integer which may be positive, to shift positively and negative to shift negatively. If the input signal is positively Doppler shifted, then to compensate one would typically rotate the vector negatively, and vice versa. This has the effect of translating the signal to near 0 frequency or some other desired frequency. The advantage of this approach is that following one forward FFT, one could test a multiplicity of Dopplers, by a series of inverse FFTs, each of which follows a frequency shift via a rotation operation. Data in the frequency domain is considered circular in the sense that the data sample following the last frequency sample is that of the first frequency sample. Hence instead of a shift, this is normally referred to as a rotation. This invention also applies to a normal shift in which zeros are appended to data as needed. For example, if 20 Doppler frequencies were tested in this manner, only one forward FFT would be required and 20 inverse FFTs would be needed, one for each Doppler to be tested. In this example only 21 FFT operations need be performed vs. 40 in the standard method. Operation 1102 is performed multiple times to provide a series of Doppler compensated frequency vectors, each of which is for one of the Doppler bins being tested.

In many cases, examining Doppler uncertainty regions in increments of integer bin spacing is coarse, resulting in a worst-case loss of sinc(0.5) or 3.9 dB. In order to reduce this loss, one would like to perform a rotation of the above vector by ½ bin spacing, that is, one would like to test for Doppler equal to m+½ bin frequency offset. This can be done in one of three ways.

In the first method, two forward FFTs are performed, one with no modification, and the second with a time domain implemented frequency shift equal to one-half bin spacing, that is a frequency offset of sample rate/(2′no_FFT_samples). This frequency offset would done in the time domain by multiplying by a complex sinusoid in the usual manner (or using an equivalent algorithm (e.g. CORDIC rotation). Each of these forward FFTs are stored. In order to test for Dopplers errors of integral number of bins, one rotates the first forward FFT vector by the required number of bins. In order to test for Doppler errors incorporating a one-half bin spacing, one selects the second forward FFT vector and rotates by an appropriate integral number of bins. For example, if one wanted to test for Doppler error of m+½ bins (m and integer), i.e. we wish an overall compensating shift of −m−½ bins, one would rotate the second forward FFT vector by −m−1 positions. Here we are note that the second FFT data set incorporates a shift of +½ bin (by assumption) so that the total shift is −m−1+½=−m−½. Of course, the above technique also works if the data used prior to the second forward FFT were first frequency offset by minus one-half bin, or in fact by one-half bin plus a positive or negative integer multiple of bins. In that case the data vector, following the second forward FFT, would need to be rotated by an appropriate integer amount to achieve the overall desired Doppler compensation.

The above first approach is extremely accurate but, of course, doubles the number of forward FFT operations. In the prior example, a total of 22 forward FFTs are required vs. the 40 FFTS in the standard approach, still a good savings. However, another disadvantage is that twice as many forward FFT vectors need to be retained, which may be costly in memory, especially if a number of parallel FFTs are required to achieve an overall acquisition time.

Referring to FIG. 16A, in the above discussion, the switches (1109,1110) pass the data from the forward FFT through the processing block 1102, but the switches (1111,1112) bypass the block 1103 (interpolation operation). The switches are put in other positions for alternative methods of these embodiments. Note that these “switches” are not necessarily hardware elements but may be viewed as flowchart decision paths.

The second approach to achieve an offset incorporating ½ bin spacing is to use an interpolation technique in the frequency domain upon the forward FFT samples to construct the intermediate samples at ½ bin spacing from each of the original frequency samples. The vector of intermediate samples then takes the place of the second forward FFT as discussed above. This vector of intermediate samples is also rotated by the required number of positions to implement a Doppler shift of M bin spacing plus the requisite number of integer bins. Many different interpolation functions may be used to determine the intermediate samples, depending upon complexity and accuracy required. For example, a sinc interpolator, i.e. sin(2πf)/(2πf) may be used where f is in units of bin spacing. Alternatives include polynomial interpolators, splines, etc. In general, the most appropriate interpolator may be determined empirically since it depends upon the frequency response of the time samples as well as the maximum complexity of the interpolator. With ½ bin spacing achieved by either method the worst-case loss due to Doppler error becomes −0.91 dB. This does not include any additional implementation errors (e.g. interpolation errors).

The above interpolation method may be viewed in FIG. 16A in which the switches 1111,1112 allow the data to be passed through the interpolate vector block 103. The switches 1109 and 1110 may in addition be used if the frequency shift is other than +/−½ bin.

In yet a third method, an interpolation is done but instead of performing it in the frequency domain, the input set of data samples is augmented, or “zero-padded”, with additional frequency samples of value zero that are appended at the beginning or end of the sample set. If the set of zero-valued samples equals that of the original set of samples, then the FFT of the resulting augmented sample set has an FFT which now has ½ bin spacing, relative to that of the nonaugmented set. Hence a simple rotation of the FFT vector now provides a frequency translation in either the positive or negative direction, in a manner similar to that discussed above. Spacing with less than ½ bin can be achieved by augmenting the original set with even more zero-valued samples (e.g. adding twice as many zero valued samples provides ⅓ bin spacing, etc.). This third method has the disadvantage that an FFT of twice the size, or larger, is required together with twice the storage required for the performance of this processing. This is probably less efficient that methods 1 and 2, although it may be competitive in some situations, particularly for relatively small FFT sizes. The zero-padding can be seen in FIG. 16A as an optional step at the input of the perform FFT block 1101.

The choice of the first versus the second approaches toward testing the Doppler with m+½ bin spacing depends upon the complexity of the interpolation vs. the storage requirements of the first approach. In terms of computational speed, one desires that the interpolator approach uses less operations per frequency sample than does the FFT. Although it may seem that an interpolation procedure is more computationally efficient, a little further examination shows that this is not so clear, particularly if only a few different Doppler frequencies are to be searched. FFT operations are extremely efficient in terms of operations per data sample. A radix-2 FFT of length N requires only approximately 2 log₂(N) real multiplies per data sample. For example, an FFT of size 1024 required only about 20 real multiplies per data sample. An equivalent complexity interpolator would have interpolation filter of length (number of taps) equal to 10, since two real multiplies are required per frequency sample. Since the frequency data tends to be very noisy, it is not clear that such a short length would be adequate for required accuracy. Note that even if one uses the first method, one would still advantageously employ the rotate vector block 1102 to reduce processing time when searching over a large range of Doppler frequencies.

The above approaches may be further generalized to offsets other than m+½ bin spacing to m+e bin spacing, where e is any number between 0 and 1. One could compute an additional forward FFT following frequency translation of input data by an amount corresponding to e bins and store this for use later, where this vector is used together with an appropriate number of vector position shifts. Alternatively, one could use interpolation methods to determine the intermediate samples from any of the precomputed FFT data sets (e.g. the set with 0 frequency offset and 1% bin offset). Again, there is the tradeoff of more forward FFTs being required and consequential storage increase, vs. the computational complexity of an acceptable interpolation method.

It should be clear from the above discussion that the three methods discussed above may be combined in a variety of ways, for example the third method may be combined with the second method to achieve very small bin spacing without requiring additional FFT operations.

In another aspect of these embodiments, tests of a set of Doppler frequencies can be done for more than one PRN, corresponding to more than one received GNSS satellite signal, without performing additional forward FFTs. That is, in the previous discussion a forward FFT, or a few forward FFTs, were performed on the data and then a set of inverse FFTs are performed to test for a variety of Doppler shifts and these all correspond to one particular satellite signal, i.e. one particular PRN. As indicated above as part of the overall processing there occurs a multiplication of the frequency samples by frequency samples of a PRN reference signal. This would occur following the Doppler shifting operating described above. This is because the PRN frequency samples are assumed to have zero frequency offset. A similar set of inverse FFTs can be performed for other PRNs, by using the corresponding frequency samples of these other PRNs, and additional Doppler frequencies can be tested, again without having to perform another forward FFT corresponding to these additional PRNs. In all the above methods the frequency altered data is multiplied by the reference data from 1105 in the multiplication block 1104, then processed by an inverse transform procedure 1106. The outputs from this may be accumulated in 1107, either predetected, or detected. Finally, the accumulated data is examined for strong correlation peaks indicative of the time of arrival of the GNSS signal with the specified Doppler and PN sequence. It is of course the case that the reference generator 1105 produces Fourier transformed PRN sequences. Such transformed sequences may be stored in memory for later use or computed on the fly.

In yet another aspect of the invention, instead of rotating or shifting the vector of frequency samples provided by the forward FFT of the signal samples, a similar operation may be done to the frequency samples of the PRN reference signal. That is, one does a Doppler compensation on the PRN frequency samples rather than on the signal frequency samples. This is illustrated in FIG. 16B. The switches 1209, 1210, 1211, 1212 allow the rotation or interpolation or both in a manner similar to the discussion of FIG. 16A.

A problem with this approach is that the resulting product of the signal frequency samples and the Doppler compensated PRN samples will no longer be at zero frequency even when the hypothesized Doppler is exactly that associated with the signal. Hence, the inverse FFT will contain a frequency offset. In order to perform multiple coherent summations of these inverse FFT vectors, one may have to first compensate the frequency offsets by a multiplication with a complex sinusoid to translate such vectors to zero frequency. However, taking the magnitude of the inverse FFT will remove the frequency offset component. Hence for applications in which one only performs noncoherent summations of these inverse FFT vectors, this approach works well. An advantage of this approach is that the Doppler shifted PRN frequency samples may be precomputed, hence eliminating any additional forward FFTs of signal data, as may be indicated with the prior mentioned approach (using Doppler shifted signal frequency samples). Of course, there is a penalty to be paid for such precomputation in terms of memory storage.

In the above description we describe the Doppler shifting as a vector rotation or a circular rotation. For small amounts of rotation, there is little loss if one can replace the rotation by a shift operation in which instead of a rotation of samples at the end of the vector to the beginning (or vice versa), one would replace the samples near the beginning (or end) with zero-valued or other value samples. The above approach still works in this case with little change in the resulting performance of the GNSS acquisition performance. As an example, if one rotated the frequency vector by 5 bins in positive direction, then such a rotation would move the last 5 elements of the vector to the first 5 elements of the vector, which would be at the most negative 5 frequency bins. If instead a shift were used, these first 5 bins would be typically replaced by zero valued data. In all cases we refer to “rotation”, or “circular rotation”, it also includes such shifting operations. Typical Doppler shifts due to GNSS satellite motion are normally in the range of +/5 kHz and typical PRN frame rates are 1 kHz. Hence the Doppler shifts due to satellite motion are normally in the range of +/−5 FFT bins. Since the FFT sizes correspond to the PRN lengths, which are typically in excess of 1000, it is the case that a frequency shift and a rotate produce similar results. We should also note that the band edges of the FFT data tend to be low in amplitude due to filtering of input data so that edge effects associated with rotation or shifting are normally minimal.

One or more embodiments can combine the approaches of frequency rotation/interpolation with reference signal rotation/interpolation. For example, the embodiments in FIGS. 16A and 16B may be combined, as illustrated in FIG. 16C with the use of the switches to facilitate the manner and type of rotation and/or interpolation.

Of course in all the above approaches one may be able to process a block of data with more than one PN reference, corresponding to more than one satellite signal, without having to perform multiple forward FFT operations. After the forward FFT operation, different PN sequences and different frequency hypotheses may be utilized upon the transformed data, each then undergoing an inverse transform without the necessity for additional forward FFT operations.

All the prior cases incorporate a term by term multiplication of the frequency data by the reference data, an inverse FFT, accumulation operation and peak detection operation, as exemplified by blocks 1104,1106,1107,1108 of FIG. 16A, 1204, 1206, 1207, 1208 of FIG. 16B and 1304, 1308, 1309, and 1310 of FIG. 16C.

For terminology clarity, we often refer to a collection of samples, whether signal samples or reference samples, as a vector, with the usual notation. When we say multiplication of vectors, where the output is a vector of similar size, the multiplication is term by term of the two vectors, sometimes called a “Hadamard” product. We sometimes used the terminology a set of function samples, which also may be considered as a vector. This multiplication may also involve a complex operation upon either the frequency samples or the reference samples.

Embodiments of Receiver Architectures

To enable flexible and power efficient sideband A or sideband B processing, a number of GNSS radio architectures are proposed, in which the overall frequency plan, the filtering, the ADC clocking and the subsequent decimation plan is modified. This configuration allows for optimum performance vs power consumption trade-offs. These architectures utilize varying degrees of digital circuit content and are described below.

FIG. 4A shows the convention used to describe the radio portion of the GNSS Receiver. This convention relates to the description of the radio architectures below and distinguishes among the RF front end components 1401 that tend to be external to the integrated circuit, the mixed-signal section 1402 that can include switches, mixers, filters, amplifiers and Local Oscillator circuits and the Analog to Digital Converter (ADC) 1403 block that provides signal sampling and quantization functionality. Any additional subsequent processing blocks are beyond the scope of the Radio Receiver as defined in FIG. 4A.

FIG. 4B shows a conventional IQ quadrature receiver architecture requiring significant analog circuit content. The signal as received by the Antenna is passed through the RF Front End 1401 which provides low noise amplification and filtering. The RF signal is then downconverted to baseband (Zero IF, or Very-Low IF) through a set of quadrature passive or active mixers 1404 and 1405, then low-pass filtered by a set of active low-pass filters (LPF) 1406 and 1407 and quantized at a given sample rate Fs by a set of quadrature ADCs 1408 and 1409. The quadrature local oscillator signal IQLO 1426 provides an I-path local oscillator signal ILO and a Q-path local oscillator signal QLO at 90-degree phase difference and each of them drives a branch of the quadrature mixer 1405 and 1406. The IQLO frequency is derived by frequency division in Frequency Divider D2 1425 of the output frequency fPLL 1421 of the RF Phase Locked Loop (RF PLL) 1420. The RF PLL 1420 synthesizes output frequency fPLL 1421 based on a reference frequency fREF 1419 obtained by a Crystal Reference Oscillator 1418. fREF 1419 is usually shared with other radio circuits on board a given device. Note that the value of D2 can be 1 or higher. In this diagram the frequency division function 1425 and the quadrature generation function 1427 are shown as two distinct blocks. Depending on the actual design they can be performed in the same block (e.g. with quadrature binary clock dividers). The signals ILO and QLO as indicated in FIG. 4B are essentially the same signal but with 90 degree phase difference. The sampling clock of frequency Fs 1423 is also derived from the RF PLL 1420 by frequency division in 1422. Clock signal 1423 is also fed to the Digital Front End block 1450 to aid further processing of the digitized signals.

The frequency plan of the IQ quadrature receiver is also illustrated in FIG. 4C. Each graph is a frequency domain representation of a signal with the horizontal axis being in frequency units while the vertical axis shows power spectral density or discrete spectral components. The first graph shows the spectrum of the desired signal at RF. The next plot down shows the location of the ILO and the Low-Pass downconverted BB-I signal with the low pass filter response indicated with a dotted line. Similarly, the QLO and downconverted low-pass Q-path signal BB-Q is also shown below.

FIG. 4D illustrates a modification in the architecture of FIG. 4B, where a switching mixer 1410 converts the RF signal at the output of the RF Front End 1401 to an intermediate frequency (IF) signal. The IF signal is then amplified and filtered with a continuous or discrete time Band Pass Filter (such as N-path) 1411 and then down-converted to low-pass baseband with a set of quadrature mixers 1404 and 1405. It is subsequently passed to a set of antialiasing active LPFs 1406 and 1407 which provide Low-Pass I and Q signals centered at Low-IF or Zero-IF to the quadrature ADCs 1408 and 1409 as described above. The receiver is time-synchronized by a single RF PLL 1420 and all clock and LO frequencies are derived by division of the fPLL 1421 signal. The RF PLL 1420 synthesizes output frequency PLL 1421 based on a reference frequency fREF 1419 obtained by a Crystal Reference Oscillator 1418. fREF 1419 is usually shared with other radio circuits on board a given device. To add flexibility, but at the cost of complexity and area, the RF-PLL 1420 can be implemented with a fractional-N divider. The Frequency Divider D1 1422 provides the sampling clock Fs 1423, the Frequency Divider D2 1425 provides the IQLO signal 1426 to the quadrature phase generator 1427. As described above the quadrature generation functionality 1427 can also be integrated with the frequency divider 1425. Alternative quadrature phase generation techniques include passive Resistor-Capacitor or Inductor-Capacitor circuits on either the IQLO path or the RF path and are well known to those skilled in the art. The RF mixer 1410 is driven by local oscillator signal RFLO 1428 which is generated by Frequency Divider D3 1427. Note that D3 can take values of 1 or higher.

The frequency plan of the architecture in FIG. 4D works around the following relationships:

-   -   1) Intermediate frequency: IF=RFLO−RF (for high-side injection)         -   IF=RF−RFLO (for low-side injection)     -   2) Baseband center frequency: fcBB=IF−IQLO (minimize for Very         Low IF, Zero IF)     -   3) RF Local Oscillator frequency: RFLO=fPLL/D3     -   4) IQ Local Oscillator frequency: IQLO=fPLL/D2     -   5) Sampling Clock frequency: Fs=fPLL/D1     -   6) Harmonic Relationship of RF and IF: IF=RF×M/L     -   7) RF PLL frequency: fPLL=(N+J/K)×fREF (assuming Fractional-N         division)         -   fPLL=N×fREF (assuming integer-N division)

If RF is related to IF via a M/L factor, then with algebraic manipulation the following relationship can be derived: RFLO=RF (1+M/L) for high-side injection and RFLO=RF(1−M/L) for low-side injection. Furthermore, since fPLL=(N+J/K)×fREF=RFLO×D3, and thus RFLO=(N+J/K)×D3×fREF. Also, in the case where a Zero-IF receiver frequency plan is pursued, IF=IQLO and since RFLO, IQLO and Fs are harmonically related via integer division to fPLL, the following relationships can be derived between D2 and D3: D2=D3×(L/M+1) for high-side injection and D2=D3×(L/M−1) for low-side injection. The frequency plan of the architecture in FIG. 4D is illustrated in FIG. 4E. As an example, a high-sided RFLO injection is illustrated.

The following table describes four frequency plan scenarios relating to a desired signal centered at 1191.795 MHz. Each scenario has different positioning of the RFLO, IF and IQLO. For example, Scenario A features a PLL frequency of 4×RFLO at 5952 MHz and places the IF at 296.2 MHz or 14 of the desired RF center frequency. Similarly, Scenario B places the fPLL at 4×RFLO and the IF at ⅓ of RF. Scenario C places the fPLL at 2×RFLO and the IF at 14 of RF, while Scenario D has the fPLL at 2× RFLO and the IF at ⅓ of RF. For each scenario, the table also lists the D2 and D1 divider values, the sampling frequency fS and the baseband signal center frequency fcBB. The location of fcBB indicates how close to a Zero-IF condition the receiver operates. In the below scenarios, an integer-N RF PLL was used with a reference frequency fREF of 19.2 MHz. Using an integer-N PLL results in slight offsets in fcBB which can be eliminated of by de-rotating the final digitally down-converted baseband signal in the Digital Front End.

fDes fPLL D3 fRFLO IF/RF fIF D2 fIQLO D1 fS fcBB Scenario MHz MHz — MHz — MHz — MHz — MHz MHz A 1191.795 5952.00 4 1488.00 1/4 296.205 20 297.6 42 141.7143 −1.395 B 1191.795 6355.20 4 1588.80 1/3 397.01 16 397.2 48 132.4 −0.195 C 1191.795 2976.00 2 1488.00 1/4 296.21 10 297.6 24 124 −1.395 D 1191.795 3187.20 2 1593.60 1/3 401.81 8 398.4 24 132.8 3.405

FIG. 4F illustrates a variation of the architecture shown in FIG. 4D where the analog LPF and mixers are replaced by a quadrature sampling arrangement. The RF signal at the output of the RF Front End 1401 is down-converted by Mixer 1410 with the aid of the RFLO signal 1428 which is derived by frequency division of the fPLL signal 1421 by the Frequency Divider D2 1427. The RF PLL 1420 synthesizes output frequency fPLL 1421 based on a reference frequency fREF 1419 obtained by a Crystal Reference Oscillator 418. fREF 1419 is usually shared with other radio circuits on board a given device. To add flexibility, but at the cost of complexity and area, the RF-PLL 1420 can be implemented with a fractional-N divider. The IF signal obtained at the output of Mixer 1410 is then amplified and filtered by a Band Pass Filter 1411 which is acting as an anti-aliasing filter. The amplified and filtered IF signal is then sampled by a quadrature ADC composed of an I-path ADC 1409 and a Q-path ADC 1408. The quadrature sampling function is achieved by a 90-degree phase difference between the two sampling clocks Fs-I and Fs-Q. This phase difference is obtained by a Quadrature Phase Generator 1424 which is implemented as a Divider-by-4 which can provide 4 distinct phases of the Fs signal. Note that the effective sampling frequency Fs is derived from signal fPLL 1421 by combining the Frequency Divider D1 with the Quadrature Phase Generator and Frequency Divider-by-4 1424. Fs is thus derived as fPLL/[D1×4]. The two quadrature sampling clocks Fs-I and Fs-Q are also provided to the Digital Front End 1450 and the two clocks are synchronized to each other by also utilizing the 4×Fs clock signal 1423. The architecture of FIG. 4F is more amenable to digital implementation since the RF mixer can be realized as a passive block with switches and resistors and the BPF can be realized as a discrete time block (e.g. N-path filter) with switches, resistors and capacitors. Larger division ratios of D1×4 (e.g. 8 or 12) also provide larger numbers of distinct phase states and can thus yield better N-path filter resolution and rejection characteristics. The quadrature ADCs are effectively sub-sampling the signal at the IF location.

The frequency plan of the architecture in FIG. 4F works around the following relationships:

-   -   1) Intermediate frequency: IF=RFLO−RF (for high-side injection)         -   IF=RF−RFLO (for low-side injection)     -   2) RF Local Oscillator frequency: RFLO=fPLL/D2     -   3) Quadrature Sampling frequency: Fs-I=Fs-Q=fPLL/(D1×4)     -   4) Harmonic Relationship of RF and IF: IF=RF×M/L     -   5) RF PLL frequency: fPLL=(N+J/K)×fREF (fractional-N divider)         -   fPLL=N×fREF (integer-N divider)

If RF is related to IF via an integer N, then with algebraic manipulation the following relationship can be derived: RFLO=RF (1+M/L) for high-side injection and RFLO=RF(1−M/L) for low-side injection. Furthermore, since fPLL=(N+J/K)×fREF=RFLO×D2, and thus RFLO=(N+J/K)×D2×fREF. Also, since in this case a true Zero-IF receiver frequency plan is preferred, a fractional PLL shall provide needed flexibility in the synthesis of fPLL. Noting that IF=Fs-I=Fs-Q and since RFLO, Fs-I, Fs-Q are harmonically related via integer division to fPLL, after some algebraic manipulation the following relationships can be derived between D1 and D2: D1=D2 (L/M+1)/4 for high-side injection and D1=D2×(L/M−1)/4.

A sketch of the frequency domain processing in the above arrangement is also shown in FIG. 4G. A high-side RFLO injection is used as an example since it offers larger image rejection through Low pass Filtering of the input signal at the RF Front End. The IF signal is Anti-Alias Filtered and the sampling clocks Fs-I and Fs-Q result in digital baseband signals BB-I and BB-Q. Note that, in contrast to signals before digitization, the BB-I and BB-Q signals are in discrete time, and as such their frequency axis is defined in radian frequency from −2pi to +2pi radians.

The following table describes four frequency plan scenarios relating to a desired signal centered at 1191.795 MHz. Each scenario has different positioning of the RFLO and IQLO. For example, Scenario A features a PLL frequency of 4×RFLO at 5958.975 MHz and places the IF at 297.949 MHz or 14 of the desired RF center frequency. Similarly, Scenario B places the fPLL at 4×RFLO and the IF at ⅓ of RF. Scenario C places the fPLL at 2×RFLO and the IF at ⅕ of RF, while Scenario D has the fPLL at 2× RFLO and the IF at ⅓ of RF. Note that all of the below scenarios utilize a fractional-N PLL which ensures the baseband frequency offset is zero, i.e. the receiver down-converts to Zero-IF. In the case where an integer PLL needs to be used with a given Crystal Oscillator Frequency fREF, slight baseband conversion frequency offsets may be observed. As mentioned above, these can be digitally down-converted to zero offset from DC.

fDes fPLL D2 RFLO IF/RF IF D1 fS Scenario MHz MHz — MHz — MHz — MHz A 1191.795 5958.975 4 1489.7438 1/4 297.949 20 297.949 B 1191.795 5720.616 4 1430.154 1/3 238.359 24 238.359 C 1191.795 2860.308 2 1430.154 1/5 238.359 12 238.359 D 1191.795 3178.12 2 1589.06 1/3 397.265 8 397.265

In yet another implementation, FIG. 4H shows a sampling architecture as realized for the GNSS system described herein. As mentioned earlier, the RF Front End 1401 is typically composed of discrete RF components (low noise amplifiers and filters) and provides a filtered and amplified signal to the Amplifier & BPF block 1411 which can be integrated in the SOC. Low noise amplifiers and selective filters often require inductors which are expensive to integrate onto the SOC and are typically located off-chip, especially if a fully digital fabrication process is utilized. After the RF signal has been sufficiently Anti-Alias Filtered through blocks 1401 and 1411, it is sampled by an RF ADC 1460. The sampled signal is down-converted/mixed by the closest sampling clock harmonic and processed by the Digital Front End 1450, which includes complex down-conversion with complex multipliers, de-rotators and similar blocks to finally yield digital complex quadrature baseband 11451 and Q 1452 signals. Although the architecture of FIG. 4H seems more amenable to integration in digital CMOS processes, it suffers from linearity and noise immunity problems. The Anti-Aliasing Filtering is achieved by the BPF in block 1411 which can be better integrated if implemented in discrete time (i.e. with some form of sampling and hold circuitry ahead of it). It is also possible to use mixed-signal technology such as N-path filters, albeit operating at very high radio frequencies and at a cost of power consumption. One approach that can save power but requires a spectrally clean clock is subsampling, where a lower frequency sampling clock creates a number of aliased bands thus downconverting a multitude of signals aliased through the various sampling harmonics. The anti-aliasing filtering function in the Amplifier & BPF 1411 is designed to ensure the unwanted aliased components (including noise) are sufficiently rejected. FIG. 4I illustrates the frequency plan of a subsampling arrangement. Two subsampling scenarios are considered. Scenario 1, uses a fundamental band-pass sampling which down-converts the RF signal to the lowest digital Nyquist band, while Scenario 2, uses a second sampling harmonic to band-pass sample the RF signal and convert it to the first image band, or to the lowest digital Nyquist band but with inverted spectrum. Note that again, the digitized IF signals are defined in discrete time and as such their frequency axis is referred to radian frequency from −2pi to 2pi.

In yet another implementation, FIG. 4J illustrates an improvement on the architecture of FIG. 4H, which suffers from low aliasing immunity due to limited selectivity and higher power consumption due to higher quality clock requirements. In a fashion similar to the architecture described in FIG. 4D, the RF signal from the Antenna passes through an external RF Front End 1401 with the appropriate amplification and band filtering, then enters a passive mixer 1410 that downconverts the signal to an intermediate frequency based on the RFLO signal which is again derived by frequency division (in Frequency Divider D2) of the fPLL signal 1421 originating at the RF PLL 1420. The IF signal at the output of the mixer 1410 is fed to an arrangement of amplification and band pass filtering in the Amplifier & BPF block 1411. The Amplifier & BPF block 1411 ensures sufficient low-noise anti-aliasing filtering is provided. It can also take advantage of discrete time signal processing techniques such as N-path filtering which can easily be realized in all-digital IC fabrication processes. The filtered output IF signal is then subsampled at the ADC 1460 which is operating at the Fs 1423 rate. This, again eases the filtering implementation requirements and also the ADC clocking requirements. By filtering an IF signal a favorable power versus performance trade-off can be obtained on the Anti-Aliasing filtering performance of the LNA & BPF block 1411 with lower clock rates and power consumption and better rejection characteristics. In addition, subsampling an IF signal, the ADC 1460 can now operate at a lower sampling rate while also ensuring less aliasing and allowing higher resolution and lower power consumption. Note that larger numbers of clock phases obtained by divisors including a factor of 4 can result in further performance improvements in an N-path filter integrated in the Amplifier & BPF block 1411. The frequency plan of the architecture in FIG. 4J is shown in FIG. 4K. Again, two scenarios are considered. In Scenario 1 the sampling and down-conversion employs the mechanism of subsampling through the higher Nyquist band of the fundamental. In Scenario 2 the sampling and down-conversion employs the mechanism of subsampling through the lower Image band of the 2^(nd) sampling harmonic. Note that the constraint of the frequency fPLL 1421 being divisible by divisor D1 1422 and also by divisor D2 1427 requires optimization of the IF placement. For hardware-efficient IF downconversion to baseband in the Digital Front End 1450, it is preferable to locate the IF at Fs/4, 3Fs/4, 5Fs/4, 7Fs/4 etc. Other locations such as Fs/8, 7Fs/8, 9Fs/8, 15Fs/8 can also work out efficiently.

The 52 MHz-wide Galileo E5 signal (frequency spectrum shown in FIG. 4O) poses interference immunity and power consumption challenges to GNSS receivers operating in this band. To mitigate interference and reduce power consumption three general possibilities are identified for the radio receiver:

(1) Selection of E5a+E5b or E5a or E5b signal processing by time-division with adaptable duty cycle for optimum power consumption (i.e. a form of time duplexing/multiplexing) (2) Selection of E5a+E5b or E5a or E5b by RF or mixed signal filtering (i.e. a form of frequency multiplexing) (3) Intentional folding of E5a on E5b, (i.e. Code-domain multiplexing) or E5a on itself or E5b on itself by using real mixing and appropriate Local Oscillator frequency location.

Aside from duty-cycling the receiver based on interference rejection, the use of different portions of the signal spectrum by selection or by folding can also reduce power consumption on the analog/RF and digital front-end in various degrees and depending on the given architecture. Since the receiver is capable of tuning to any of the two sidebands it can be operated in the following ways:

-   -   (1) The upper (E5b) or lower (E5a) sideband is selected and         processed at half rate (20×1.023 MHz) compared to the full 52         MHz band. As an example, the selection of the E5B sideband is         shown in FIG. 4P.     -   (2) The upper (E5b) or lower (E5a) sideband is selected and         processed. In addition, the processing can be duty-cycled for         optimum power consumption.     -   (3) The upper (E5b) sideband is selected and if excessive         DME/TACAN interference is detected the receiver switches to the         lower (E5a) sideband. The converse can also happen.     -   (4) Both sidebands are folded on each-other by using a real         mixing operation as explained below.     -   (5) The upper (E5b) or lower (E5a) sideband is selected and         processed at half rate (20×1.023 MHz) also at half the low-pass         bandwidth (e.g. 12 MHz) by folding the sideband on itself and by         using a real mixing operation as explained below.

The E5a vs E5b selection can happen in real time or in predetermined fashion as described above. Radio receiver architectures such as the ones shown in FIGS. 4B, 4D and 4F allow flexible processing by switching between a double sideband and a single sideband signal, while making performance and power trade-offs. The receiver configuration includes changing the RFLO and IQLO frequencies appropriately and if applicable, modifying the pass-band of the filters.

Real mixing results in folding a bandpass desired signal on itself by using a single mixer and by placing the local oscillator frequency within the operating bandwidth of the desired signal. In the case of folding the two sidebands E5a and E5b on each other, real mixing results in a form of code domain multiplexing. To illustrate this concept the radio architecture of FIG. 4B is configured as shown in FIG. 4L, where the Q-path of the quadrature mixer, LPF and ADC are shut down. The Local Oscillator ILO 426 frequency remains at 1191.795 MHz. Referring to the analysis shown in Appendix 3, at the output of the mixer 405, the two sidebands, E5a and E5b are converted to baseband and folded over each other, furthermore E5a is spectrally reversed. The Low-Pass bandwidth of the folded signal in the single real-path is still the same as before, namely 26 MHz. Also the corner frequency of the anti-aliasing LPF 407, as well as the sampling rate of the ADC 409 remain the same as in the double-sideband case. Although it carries both sidebands folded on each other, the resulting signal is not fully at baseband, but is centered at a frequency offset of 15.345 MHz. At the Digital Front End further processing down-converts the signal at zero-frequency and de-spreads one or the other sideband. The processing gain is assumed to hold well over inversed codes. Since the mixer output noise is increased by 3 dB this implementation assumes reasonable SNR margins. This technique can also reduce the receiver processing load and power consumption, especially in the architectures of FIGS. 4B, 4D, 4F as they are re-configured to operate respectively as in FIGS. 4L, 4M, 4N.

Real mixing in the case of folding a given sideband (E5a or E5b) on itself, the local oscillator is placed close to the center of the sideband (1176.450 MHz for E5a, 1207.140 MHz for E5b), while also reducing the low pass bandwidth to much less than 26 MHz (since due to the folding to the negative frequency axis the effective bandwidth is now double-sided). The folding results in a 3 dB SNR degradation, but since each sideband is spread by a pseudorandom code with sufficient coding gain, the spread signal can still be retrieved. Depending on the frequency tracking loop bandwidth, a small frequency offset (e.g. 10 kHz or more) may need to be applied to the local oscillator signal so that the negative folded spectrum does not interfere with receiver synchronization. This technique results in significant radio power reduction, especially in the architectures of FIG. 4B, 4D, 4F as they are re-configured to operate respectively as in FIGS. 4L, 4M, 4N. In addition, further interference immunity is achieved by reducing the effective receiver bandwidth, compared to full double-sideband operation.

One way to save power consumption during tracking, is to use a single sideband as this reduces the clock rate requirements in the Digital Front End and subsequent stages. In one particular implementation, during acquisition the full double sideband signal (E5a and E5b sidebands) is processed by operating the full complex radio receiver (as shown in FIG. 4B) and a complex 52 MHz bandwidth is processed (2× real 26 MHz bandwidth). The Low pass filter bandwidth, ADC clock and decimation plan are accommodating a wideband signal as shown in the frequency spectrum of the E5A or E5B signals. When the receiver enters tracking mode the radio receiver is configured according to FIG. 4L in which the 2× real 26 MHz bandwidth is processed by a single mixer resulting 26 MHz complex signal bandwidth offset to a 15.345 MHz IF but also carrying the two sidebands folded on each other. As mentioned above, although the architecture in FIG. 4B is especially suitable for this feature, other architectures are also applicable. In particular, the radio architecture described in FIG. 4D can be configured as in FIG. 4M. In addition, the radio architecture described in FIG. 4F can be configured as in FIG. 4N.

FIG. 17 shows an example of a method that switches between use of a plurality of signal components during acquisition and use of a subset of those acquired signal components during tracking after successfully acquiring at least one signal component from a GNSS SV. This method can save power by reducing power consumption in the digital processing of received GNSS signals and potentially (depending on the implementation) in the RF portion of the GNSS receiver. It is often the case that the acquisition phase lasts only a short period of time while the tracking phase lasts a much longer period of time; reducing power consumption during tracking can significantly improve the performance of the GNSS receiver (at least with regard to its power consumption specifications). Referring now to the method in FIG. 17. in operation 1701 the GNSS receiver can begin acquiring GNSS signals; for example, the GNSS receiver can use one of the receiver architectures described above (e.g., FIG. 4M or 4N) to acquire GNSS signals using, for example, the acquisition array processor described herein (e.g., see FIGS. 6-8). In operation 1703, the GNSS receiver can attempt to acquire a plurality of GNSS signal components from one or more GNSS SVs during the acquisition phase. For example, during the acquisition phase in operation 1703 the GNSS receiver can attempt to acquire 4 signal components from a GNSS SV in the Galileo constellation (e. g., the E5AI, E5AQ, E5BI, and the E5BQ signal components from a particular SV in the Galileo constellation). Normally, the GNSS receiver (at least in a “cold start” case) will attempt to acquire, in operation 1703, a plurality of signal components from a sufficient number of GNSS SVs (e.g., at least 4 or 5 SVs) to permit a position to be determined. After one or more signal components have been acquired, as determined in operation 1705, the GNSS receiver can select or determine, in operation 1707, a subset of the successfully acquired signal components to be tracked; hence, rather than tracking all of the successfully acquired signal components (that were determined in operation 1705 to have been successfully acquired), the GNSS receiver selects a subset of the successfully acquired signal components and tracks, in operation 1709, only those in the subset. For example, in a case where the GNSS receiver has acquired all 4 signal components from a first SV in the Galileo constellation (e. g., the E5AI, E5AQ, E5BI, and the E5BQ signal components from the first SV in the Galileo constellation) and has acquired 2 signal components from a second SV in the Galileo constellation (e. g., the E5BI and the E5BQ signal components from the second SV in the Galileo constellation), the GNSS receiver can select to track only one or the four signal components from the first SV and one of the two signal components from the second SV during the tracking phase. Those signal components that were not selected will not be tracked, thereby reducing power consumption in the GNSS receiver. The selection in operation 1707 can attempt to select the “best” signal component to be tracked, and some examples of possible selection criteria or algorithms are provided below. In one embodiment, “best” may be near optimal instead of truly optimal because near optimal can still reduce power consumption while still providing acceptable tracking.

The best sideband can be chosen with one or more of the following algorithms:

-   -   1) The sideband with the least interference. Often the DME/TACAN         will be seen in only one sideband. The best sideband is the one         without the current DME interference. Later in a different area,         the interference may be dominant in a different sideband.     -   2) The sideband with the most launched satellites. Currently the         lower sideband centered at 1176.45 Mhz has the most satellites:         namely US L5, China B2a, Japan QZSS L5, and Europe E5a. Thus,         the upper sideband can be disabled after acquisition.     -   3) The sideband with the most visible satellites at the current         time and location as determined by computing the elevation angle         of all launched satellites. The visible satellites have a         positive elevation angle above the horizon and secondly above a         non-zero mask angle, such as 10 degrees. It is possible that at         a given time, one sideband may contain more satellites than the         other.     -   4) The sideband with the fast data rate when the receiver has         not yet determined fine time. For example, the upper sideband of         B2 has a 1 kHz data rate vs 200 Hz on the lower sideband, the         upper sideband of E5 has a data rate of 250 Hz vs a 50 Hz on the         lower sideband. The faster decode of a time stamp allows a gain         in accuracy by learning fine time.     -   5) A plurality of these “best” sidebands can change dynamically,         for example, start with the data decode, then transition to most         visible, and then modulate in case of interference.     -   6) The sideband that contains the satellites of a chosen         constellation that is required in a particular country based on         import restrictions. For example, if Russia requires use of         Russian L5 satellites, and they are placed exclusively in one         sideband, then that sideband would be the best single tracking         sideband based on import requirements.

Spoofing may be seen at one sideband and not at the other. If the receiver is able to process each system independently, identify spoofing, where an independent fix with one constellation identifies spoofing, and the best sideband for the non-spoofed constellations is identified.

To reduced power consumption, tracking can be performed on a best sideband rather than multiple sidebands from the same GNSS SV. This implies that the RF and digital processing for the non-best sideband can be turned off, reducing power consumption. For example, RF mixer, filters, A2D, digital front end can be disabled for this other sideband. The baseband correlation can also be disabled.

After acquisition of enough SVs and determination of at least one secondary code, a fix allows determination of the remaining secondary codes and thus, a nearly direct acquisition of the remaining satellites with a significantly narrower code search. In this case, the acquisition engine can be turned off. Tracking can recover from system loss by coherent tracking of the pilot channel. Thus, the extra sideband (that is not tracked) is less critical.

Exemplary Embodiments

The following text presents numbered embodiments in claim like format, and it will be understood that these embodiments may be presented as claims in one or more future filings, such as one or more continuation or divisional applications. Although separate embodiments are described in detail below, however, it is appreciated that these embodiments may be combined or modified, in part or in whole. At least some of these numbered embodiments were presented as claims in a prior provisional application.

Embodiment 1. A system comprising:

a set of one or more application processors (APs) configured to execute an operating system (OS) and one or more application programs, the set of one or more application processors implemented in an integrated circuit (IC);

a set of one or more buses coupled to the set of one or more APs, the one or more buses on the IC;

a cache memory on the IC and coupled to the set of one or more buses and coupled to the set of one or more APs to store data for use by the OS and for use by the one or more application programs;

a bus interface coupled to the set of one or more buses, the bus interface to couple the set of one or more APs to dynamic random access memory (DRAM) which is external to the IC;

a GNSS processing system implemented on the IC, the GNSS processing system comprising an acquisition engine (AE) and a tracking engine (TE), the GNSS processing system coupled to a shared memory through the one or more buses, the shared memory being one or both of (a) the cache memory or (b) other memory on the IC;

a memory controller coupled to the shared memory and to the GNSS processing system, the memory controller to allocate a portion of the shared memory for use by the AE in response to one or more instructions from the operating system in order to allow GNSS signals to be acquired.

Embodiment 2. The system as in embodiment 1 wherein the shared memory comprises SRAM (static random access memory) and the AE includes ASIC hardware logic for performing fast Fourier transform (FFT) operations using a decimation in time method.

Embodiment 3. The system as in embodiment 2 wherein the GNSS processing system includes a dedicated memory that is separate from the shared memory and is dedicated for use by the GNSS processing system and wherein the other memory is a processor local storage for a processor that is not one of the one or more APs.

Embodiment 4. The system as in embodiment 1 wherein the memory controller includes a first port controller to control reading from and writing to the portion for the AE and a second port controller to control reading from and writing to a remaining portion of the shared memory.

Embodiment 5. The system as in embodiment 3 wherein the AE performs an acquisition of GNSS signals from GNSS space vehicle(s) (SVs) and the acquisition comprises determining frequencies of received GNSS signals containing pseudorandom codes to enable tracking of the GNSS signals to produce, as a result of the tracking, pseudoranges to the GNSS SVs.

Embodiment 6. The system as in embodiment 5 wherein the shared memory has a first port for use when the portion is allocated for use by the AE and a second port for use by either the processor or the one or more APs when the portion is allocated.

Embodiment 7. The system as in embodiment 5 wherein the allocated portion is to store one or more of: (1) pseudorandom codes of GNSS SVs or (2) hypotheses of identifiers of potentially acquired GNSS signals and hypotheses of their frequencies.

Embodiment 8. The system of embodiment 7 wherein the memory controller is to deallocate the portion after the GNSS processing system begins to track GNSS signals that have been acquired from at least three (3) GNSS SVs.

Embodiment 9. The system of embodiment 8 further comprising:

an antenna input to receive GNSS signals in an L5 WB frequency band;

a low noise amplifier (LNA) coupled to the antenna input to amplify the GNSS signals;

a radiofrequency analog to digital converter (ADC) coupled to an output of the LNA, the radiofrequency ADC and the LNA to receive and process GNSS signals in the L5 WB frequency band and wherein the GNSS processing system is configured to process only GNSS signals in the L5 WB frequency band.

Embodiment 10. The system as in embodiment 1 wherein the one or more APs, prior to or during an acquisition phase, generate GNSS pseudorandom codes for at least GNSS SVs that are in view of the system, the generated GNSS pseudorandom codes initially stored in the DRAM which is external to the IC and then copied into the shared memory during the acquisition phase or at the beginning of the acquisition phase.

Embodiment 11. The system as in embodiment 10 wherein the one or more APs generate the GNSS pseudorandom codes in a background operation only for healthy GNSS SVs that are in view or will be in view within a period of time, and wherein the OS reserves a portion of the shared memory for use by the AE in response to the one or more APs receiving a request to provide location data.

Embodiment 12. A method for operating a system, the method comprising:

receiving, from one or more application processors (APs) on an integrated circuit (IC), a request to generate location data through use of a GNSS processing system on the IC, the GNSS processing system including an acquisition engine (AE) that is configured to acquire a plurality of GNSS signals, each of the GNSS signals transmitted from one of a constellation of GNSS space vehicles (SVs);

identifying a portion of a shared memory on the IC and allocating, in response to the request, the portion for use by the AE while one or more other processors are allocated a remaining portion of the shared memory, the allocating performed by an operating system that executes on the one or more APs or by firmware executing on the IC;

storing, by the AE or the one or more APs, data related to GNSS signal acquisition processing in the allocated portion.

Embodiment 13. The method as in embodiment 12 wherein the shared memory comprises SRAM (static random access memory) on the IC and the AE includes ASIC hardware logic for performing fast Fourier transform (FFT) operations using a decimation in time method.

Embodiment 14. The method as in embodiment 13, wherein the method further comprises: deallocating the allocated portion after the GNSS processing system begins to track GNSS signals that have been acquired from at least three (3) GNSS SVs, the deallocating in response to acquiring, before a tracking phase, the GNSS signals from the at least three (3) GNSS SVs.

Embodiment 15. The method as in embodiment 14 wherein the GNSS processing system includes a dedicated memory that is separate from the shared memory and is dedicated for use by the GNSS processing system.

Embodiment 16. The method as in embodiment 14 wherein a memory controller, coupled to the shared memory, includes a first port controller to control access to the allocated portion for the AE and a second port controller to control access to a remaining portion of the shared memory.

Embodiment 17. The method as in embodiment 14, wherein the AE performs an acquisition of GNSS signals from GNSS SVs and the acquisition comprises determining frequencies of received GNSS signals containing pseudorandom codes to enable tracking of the GNSS signals to produce, as a result of the tracking, primary code phases to the GNSS SVs.

Embodiment 18. The method as in embodiment 17 wherein the allocated portion is to store one or more of: (1) pseudorandom codes of GNSS SVs or (2) hypotheses of identifiers of potentially acquired GNSS signals and hypotheses of their frequencies.

Embodiment 19. The method as in embodiment 13 wherein the one or more APs generate, prior to or during an acquisition phase, GNSS pseudorandom codes for at least GNSS SVs that are in view of the system, the generated GNSS pseudorandom codes initially stored in the system's DRAM memory which is external to the IC and then copied into the shared memory during the acquisition phase or in response to a request for location.

Embodiment 20. The method as in embodiment 19 wherein the one or more APs generate the GNSS pseudorandom codes in a background operation only for healthy GNSS SVs that are in view or will be in view within a period of time and wherein the system reserves the portion of the shared memory for use by the AE by determining data in the cache memory that is stored in non-volatile memory.

Embodiment 21. A non-transitory machine readable medium storing executable program instructions which when executed by a data processing system cause the data processing system to perform a method as in any one of embodiments 12-20.

Embodiment 22. A data processing system comprising:

a set of one or more application processors APs to execute an operating system and one or more application programs;

a set of one or more buses coupled to the set of one or more application processors;

a dynamic random access memory (DRAM) coupled to the set of one or more application processors through the set of one or more buses;

a GNSS processing system on an integrated circuit (IC) which includes a cache memory that is on the IC and is coupled to the GNSS processing system, the GNSS processing system coupled to the set of one or more application processors, the GNSS processing system comprising an acquisition engine (AE) and a tracking engine (TE);

the set of one or more application processors to receive a request for location data and, generate GNSS pseudorandom codes for GNSS Space Vehicles (SVs) for use by the AE, the generated GNSS pseudorandom codes stored in the DRAM and then copied to the cache memory for use by the AE during an acquisition phase.

Embodiment 23. The data processing system as in embodiment 22 wherein the generated GNSS pseudorandom codes are generated in response to the request.

Embodiment 24. The data processing system as in embodiment 22 wherein the cache memory comprises SRAM (static random access memory) and the AE includes ASIC hardware logic for performing fast Fourier transform (FFT) operations using a decimation in time method.

Embodiment 25. The data processing system as in embodiment 24 wherein the one or more APs generate, prior to or during an acquisition phase, the GNSS pseudorandom codes for at least GNSS SVs that are in view of the data processing system.

Embodiment 26. The data processing system as in embodiment 25 wherein the one or more APs generate the GNSS pseudorandom codes only for healthy GNSS SVs that are in view or will be in view within a period of time.

Embodiment 27. The data processing system as in embodiment 26, the data processing system further comprising:

an antenna input to receive GNSS signals in an E5 frequency band;

a low noise amplifier (LNA) coupled to the antenna input to amplify the GNSS signals;

a radiofrequency analog to digital converter (ADC) coupled to an output of the LNA, the radiofrequency ADC and the LNA to receive and process GNSS signals in the E5 frequency band, and wherein the data processing system is configured to process only GNSS signals in the E5 frequency band.

Embodiment 28. The data processing system as in embodiment 27 wherein the AE performs an acquisition of GNSS signals from GNSS SVs and the acquisition comprises determining frequencies of received GNSS signals containing pseudorandom codes to enable tracking of the GNSS signals to produce, as a result of the tracking, pseudoranges to the GNSS SVs and wherein the generated GNSS pseudorandom codes comprise GNSS pseudorandom codes that are shifted in frequency or time or both to generate a code spectrum for use by the AE during the acquisition phase.

Embodiment 29. The date processing system as in embodiment 28 wherein an allocated portion of the cache memory, during the acquisition by the AE, stores hypotheses of identifiers of potentially acquired GNSS signals and hypotheses of their frequencies.

Embodiment 30. A GNSS processing system comprising:

an antenna input to receive GNSS signals in an E5 frequency band;

a low noise amplifier (LNA) coupled to the antenna input to amplify the GNSS signals,

a radiofrequency (RF) analog to digital converter (ADC) coupled to an output of the LNA, the RF ADC and the LNA to receive and process GNSS signals in the E5 frequency band;

a circular memory buffer coupled to an output of RF ADC to receive and store digitized GNSS sample data, the circular memory buffer storing more than 1 millisecond of digitized GNSS sample data and less than 2 milliseconds of digitized GNSS sample data.

Embodiment 31. The GNSS processing system as in embodiment 30 wherein the circular memory buffer stores the digitized GNSS sample data in an array of rows and columns, and the sample data is in rows order which is also in time order, where 1 millisecond is the frame duration of the primary codes of a modernized GNSS signal, which is further covered by a secondary code at a 1 KHz rate.

Embodiment 32. The GNSS processing system as in embodiment 31 further comprising:

a GNSS processor that comprises an acquisition engine and a tracking engine, the acquisition engine comprising a set of DFT ALUs that process the digitized GNSS sample data in the array and produces an intermediate output that requires no transposing of data in the array.

Embodiment 33. The GNSS processing system as in embodiment 32 wherein a first group of DFT ALUs in the set of DFT ALUs use a decimation in time method to produce the intermediate output stored in a variable memory and a second group of DFT ALUs in the set of DFT ALUs use the intermediate output to produce an output stored in FFT result memory.

Embodiment 34. The GNSS processing system as in embodiment 33 wherein the circular memory buffer comprises a first circular memory buffer to store an A sideband in an E5 frequency band and a second circular memory buffer to store a B sideband in the E5 frequency band.

Embodiment 35. A method for processing GNSS signals in a GNSS receiver, the method comprising:

determining an initial set of information that includes at least two of: (a) a code phase of a received primary or secondary code signal from at least one GNSS Space Vehicle (SV), (b) an estimated GNSS time based on one or more sources of time, the estimated GNSS time being estimated or known to be within less than +/−0.5 milliseconds of actual GNSS time; and (c) an approximate location of the GNSS receiver;

estimating, based on the initial set of information, an expected fractional primary code phase for GNSS signals to be received;

performing a first DFT correlation using at least a first full primary code epoch of digitized GNSS sample data received over a period of time that is comparable to a time period of a code epoch of the GNSS signals, the first FFT based correlation using digitized GNSS sample data that begins at a first time;

performing a second DFT correlation using at least a second full code epoch of received digitized GNSS sample data which include at least some of the received GNSS sample data in the first full code epoch, the second DFT correlation using digitized GNSS sample data that begins at a second time that is after the first time and is offset from the first time by less than the time period of the code epoch;

removing a secondary code from results of the first DFT correlation and the second DFT correlation to provide inputs for coherent integration operation;

integrating at least one of these inputs into coherent hypothesis memory;

squaring or taking the magnitude of the results from the coherent hypothesis memory to acquire a GNSS signal from at least one GNSS SV.

Embodiment 36. The method as in embodiment 35 wherein I and Q data are summed within each of the first full code epoch and the second full code epoch.

Embodiment 37. The method as in embodiment 35 further comprising:

summing the squared results in non-coherent hypothesis memory and wherein the summing of the squared results occurs several milliseconds after the first time.

Embodiment 38. The method as in embodiment 35 wherein the method further comprises: establishing a search order for GNSS signals from GNSS SVs, the search order based, at least in part, on the expected fractional primary code phase.

Embodiment 39. The method as in embodiment 35 wherein the method further comprises: selecting a subset of the correlation hypotheses within a window including the expected fractional code phase for saving in coherent hypothesis memory.

Embodiment 40. The method as in embodiment 35 wherein the method further comprises:

assigning each SV to an input sample offset group according to, among several factors, that SV's expected primary code phase.

Embodiment 41. The method as in embodiment 40 wherein the method further comprises: assigning one SV to one estimated code epoch and assigning another SV to another estimated code epoch, wherein each SV is assigned to a code epoch that is nearer in time to the code epoch for that SV.

Embodiment 42. A method for processing GNSS signals, the method comprising:

receiving GNSS signals;

digitizing the received GNSS signals and providing an output, from an analog to digital converter (ADC), of GNSS sample data which includes at least one of (1) GNSS sideband A sample data for a received GNSS signal and (2) GNSS sideband B sample data for the received GNSS signal;

computing at least one of (1) a first set of DFTs of the GNSS sideband A sample data to provide a first set of results and (2) a second set of DFTs of the GNSS sideband B sample data to provide a second set of results;

computing at least one of (1) a third set of DFTs of GNSS sideband A primary PRN code data which is adjusted for code Doppler and carrier Doppler prior to the third set of DFTs, the GNSS sideband A primary PRN code data including at least one of two components in the GNSS sideband A, the third set of DFTs providing a third set of results and (2) a fourth set of DFTs of GNSS sideband B primary PRN code data which is adjusted for code Doppler and carrier Doppler prior to the fourth set of DFTs, the GNSS sideband B primary PRN code data including at least one of two components in the GNSS sideband B, the fourth set of DFTs providing a fourth set of results;

computing at least one of (1) a first set of correlations using a DFT of the complex conjugate of a product of the first set of results and the complex conjugate of the third set of results to provide a fifth set of results and (2) a second set of correlations using a DFT of the complex conjugate of a product of the second set of results and the complex conjugate of the fourth set of results to provide a sixth set of results;

integrating at least one of (1) the fifth set of results with at least one prior sum for the GNSS sideband A and (2) the sixth set of results with at least one prior sum for the GNSS sideband B, wherein the integrating includes at least one of (1) storing at least one new sum for GNSS sideband A components in a single hypothesis memory and (2) storing at least one new sum for GNSS sideband B components in the single hypothesis memory.

Embodiment 43. The method as in embodiment 42 wherein the fourth set of results include IDFT results for both components of the GNSS sideband A and the sixth set of results include IDFT results for both components of the GNSS sideband B.

Embodiment 44. The method as in embodiment 43 wherein the GNSS sideband A sample data is stored in a first circular memory buffer and the GNSS sideband B sample data is stored in a second circular memory buffer.

Embodiment 45. The method as in embodiment 44 wherein the GNSS sideband A sample data is stored in the first circular memory buffer in a format of an array of rows and columns and the GNSS sideband B sample data is stored in the second circular memory buffer in the format of the array of rows and columns.

Embodiment 46. The method of embodiment 45 wherein the GNSS sample data is processed to separate the GNSS sideband A sample data from the GNSS sideband B sample data by: (1) for the GNSS sideband A, shifting samples centered at a first frequency up by a first offset frequency and performing a low pass filter to capture a first bandwidth of data and deciminating the output of the low pass filter to a lower sample rate; and (2) for the GNSS sideband B, shifting samples centered at the first frequency down by the first offset frequency and performing a low pass filter to capture a second bandwidth of data and deciminating the output of the low pass filter to a lower sample rate.

Embodiment 47. The method as in embodiment 45 wherein the computing operations require no separate operations to transpose or rearrange the sample data or the generated code spectrum data at inputs to the first and second sets of correlations.

Embodiment 48. The method as in embodiment 45 wherein a code generator generates at least one of (1) the GNSS sideband A primary PRN code data every millisecond while GNSS signals are being acquired and tracked and the GNSS sideband A primary PRN code date is not stored after Fourier transformation is completed, and (2) the GNSS sideband B primary PRN code data every millisecond while the GNSS signals are being acquired and tracked and the GNSS sideband B primary PRN code data is not stored after Fourier transformation is completed.

Embodiment 49. The method as in embodiment 48 wherein the integrating is non-coherent during at least a portion of an acquisition phase while the GNSS signals are received.

Embodiment 50. A system for processing GNSS signals, said system comprising:

a radiofrequency analog to digital converter (ADC) to generate a digital representation of received GNSS signals;

a baseband sample memory to store the digital representation of the received GNSS signals as digitized GNSS sample data, the baseboard sample memory configured to store an array of the digitized GNSS sample data in N2 rows and N1 columns, the digitized GNSS sample data in the array being stored in row order in the baseband sample memory and N2 being larger than N1, the row order containing the digitized GNSS sample data that was received over a time period that includes a first time period and a second time period such that a first row in the row order contains digitized GNSS sample data received during the first time period and a second row, which follows the first row in the row order, contains digitized GNSS sample data received during the second time period that follows, in time, the first time period, the baseband sample memory coupled to the radiofrequency ADC;

a set of arithmetic logic units (ALU) configured to perform discrete Fourier transform (DFT) operations, the set of ALUs coupled to the baseband sample memory, the set of ALUs configured to perform, in parallel and concurrently in time, N1 DFTs, wherein each of the N1 DFTs contains N2 points in the DFT and the outputs of the N1 DFTs are stored in a partial result sample array, and wherein the set of ALUs are configured to then perform N2 DFTs, each of the N2 DFTs containing N1 points from the partial result sample array, the N2 DFTs providing an output stored in an DFT result array that is arranged in column order.

Embodiment 51. The system as in embodiment 50 wherein the baseband sample memory is configured as a circular memory buffer that stores the array.

Embodiment 52. The system as in embodiment 51 wherein the N1 DFTs use the same operations and same program control instructions for the set of ALUs to operate on different data.

Embodiment 53. The system as in embodiment 52 wherein the N2 DFTs are performed consecutively over time and wherein the circular memory buffer stores more than one frame of pseudorandom GNSS codes which is more than 1 millisecond.

Embodiment 54. The system as in embodiment 52 wherein the N1 DFTs and the N2 DFTs use a decimation in time method and wherein N1 is one of the integer values: 5 or 10 or 20 or 40.

Embodiment 55. The system as in embodiment 52 wherein a change from row order to column order avoids a re-ordering algorithm, the change produced by a combination of the N1 DFTs followed by the N2 DFTs.

Embodiment 56. The system as in embodiment 52 wherein a GNSS code generator is configured to generate a GNSS code, and the set of ALUs performs a set of DFTs on the GNSS code to provide a code spectrum result data stored in a code spectrum memory in a column order, the code spectrum result data including GNSS PRN code data that is frequency and/or time shifted.

Embodiment 57. The system as in embodiment 56 wherein the set of ALUs is configured to multiply the code spectrum result data by the output stored in the DFT result array to produce a product array.

Embodiment 58. The system as in embodiment 57 wherein the set of ALUs is configured to perform an inverse DFT on the product array using a decimation in frequency method.

Embodiment 59. The system as in embodiment 58 wherein the inverse DFT comprises: (1) in a first stage, N2 DFTs with conjugated inputs, each of the N2 DFTs containing N1 points, and (2) in a second stage that follows the first stage, N1 DFTs, each of the N1 DFTs containing N2 points.

Embodiment 60. The system as in embodiment 51 wherein the baseband sample memory is a dual port memory.

Embodiment 61. The system as in embodiment 56 wherein the GNSS code generator generates a pseudorandom code for each GNSS SV in view every millisecond when it is needed during an acquisition phase and does not store a generated pseudorandom code after it is used, and the generated pseudorandom code is used to generate the GNSS code spectrum.

Embodiment 62. The system as in embodiment 61 wherein the GNSS code spectrum is aligned in place in memory in both frequency and phase to match code phase and frequency shift hypotheses associated with the received GNSS signals.

Embodiment 63. The system as in embodiment 62 wherein the alignment is performed by CORDIC hardware.

Embodiment 64. A system as in embodiment 50 in which the digitized GNSS sample data is stored in column order rather than row order.

Embodiment 65. A system for processing GNSS L5 band signals, the system comprising:

a radiofrequency analog to digital converter (ADC) to generate a digital representation of received GNSS signals;

a baseband sample memory to store the digital representation of the received GNSS signals, the baseband sample memory coupled to the ADC;

a GNSS processing system coupled to the baseband sample memory to process the digital representation of the received GNSS signals, the GNSS processing system configured to process four (4) GNSS signal components of a GNSS signal to non-coherently integrate all four GNSS signal components to generate and store the non-coherent integration data for each of the four GNSS signal components into a single hypothesis memory to acquire GNSS signals.

Embodiment 66. The system as in embodiment 65 wherein the single hypothesis memory is less than 2 megabytes of memory and wherein the four GNSS signal components include a Galileo E5AI signal component, a Galileo E5BI signal component, a Galileo E5BQ signal component, and a Galileo E5AQ signal component or four GNSS signal components used in a Beidou/Compass B2 system or both of the Galileo E5 and Beidou/Compass B2 signal components.

Embodiment 67. The system as in embodiment 66 wherein the GNSS processing system processes received GNSS signal from at least two GNSS constellations including: the Galileo E5 constellation of GNSS SVs; an L5 GPS constellation of GNSS SVs, a Glonass K2 constellation of GNSS SVs, a QZSS constellation of GNSS SVs, and a Beidou B2 constellation of GNSS SVs.

Embodiment 68. The system as in embodiment 65 further comprising:

a code generator to generate GNSS PRN codes during acquisition and tracking of GNSS signals without storing the GNSS PRN codes after tracking is completed.

Embodiment 69. The system as in embodiment 68 wherein the code generator generates more than two primary PRN code bits in a clock cycle during the acquisition and tracking.

Embodiment 70. The system as in embodiment 69 wherein the code generator generates the more than two primary PRN code bits in a clock cycle by a computation that uses a computed code advance matrix derived from an N times multiplication of a code polynomial matrix for a given GNSS constellation and GNSS signal component in that GNSS constellation, N representing a number of primary PRN code bits generated in a clock cycle.

Embodiment 71. The system as in embodiment 70 wherein the GNSS processing system shares a memory with one or more processors, and the GNSS processing system, the cache memory and the one or more application processors are all disposed on a same single integrated circuit.

Embodiment 72. The system as in embodiment 71 wherein the GNSS processing system includes an acquisition engine and a tracking engine, and the acquisition engine includes processing logic to receive an array of GNSS sample data, arranged, according to time of receipt, in either row order or column order, and the processing logic to perform DFTs using a decimation in time algorithm on the array of GNSS sample data to produce frequency domain results that are multiplied by a code spectrum of GNSS PRN codes for GNSS SVs in view, and the resulting product of the frequency domain results and the code spectrum is then processed in the processing logic by IDFTs using a decimation in frequency algorithm to produce hypotheses of possible acquired GNSS signals that are accumulated non-coherently in the single hypothesis memory.

Embodiment 73. The system as in embodiment 72 wherein the array of GNSS sample data is stored in two circular memory buffers that comprise a first circular memory buffer to store A-band GNSS sample data and a second circular memory buffer to store B-band GNSS sample data, wherein a plurality of GNSS constellations may be received in at least one said band.

Embodiment 74. The system as in embodiment 70 wherein a GNSS primary PRN code from an output of the code generator is shifted in frequency and is shifted in time before applying a set of DFTs using a decimation in time algorithm to generate a code spectrum that is multiplied by frequency domain results from a set of DFTs, using a decimation in time algorithm, on a received GNSS signal.

Embodiment 75. The system as in embodiment 73 wherein a GNSS primary PRN code from an output of the code generator is shifted in frequency and is shifted in time to generate the code spectrum.

Embodiment 76. The system as in embodiment 72 wherein an order in the array changes through a sequence of the DFTs such that no transposing or rearranging of data is required when the IDFTs are performed.

Embodiment 77. The system as in embodiment 76 wherein the sequence of DFTs avoids using memory or processing resources that would be used for the transposing or rearranging.

Embodiment 78. A system for processing GNSS signals; the system comprising:

an analog to digital converter (ADC) to generate a digital representation of received GNSS signals;

a baseband sample memory to store the digital representation of the received GNSS signals, the baseband memory coupled to the ADC;

a GNSS processing system coupled to the baseband sample memory to process the digital representation of the received GNSS signals, the GNSS processing system to acquire up to four GNSS signal components of a GNSS signal by non-coherently integrating, over a period of time in an array processing system, up to four GNSS signal components, the array processing system being in an acquisition engine in the GNSS processing system and the array processing system receiving GNSS sample data from the baseband memory and the GNSS sample data being formatted in a row and column array having a plurality of rows and a plurality of columns.

Embodiment 79. The system as in embodiment 78 wherein the array processing system comprises processing logic that performs a set of DFTs using a decimation in time algorithm followed by a set of inverse DFTs using a decimation in frequency algorithm.

Embodiment 80. The system as in embodiment 79 wherein an output from the array processing system provides frequency and GNSS SV identifiers for storage in hypothesis memory to integrate hypotheses for GNSS signals.

Embodiment 81. The system as in embodiment 78 wherein the array processing system receives the GNSS sample data in a first order and produces an output in a second order that is different than the first order, and wherein the first order is one of a row order or a column order in the row and column array and the second order is one of the row order or the column order, and wherein the first order and the second order are based on the time of receipt of the GNSS sample data.

Embodiment 82. The system as in embodiment 81 wherein the GNSS sample data is stored in the row and column array in two circular memory buffers that comprise a first circular memory buffer to store a first GNSS signal component from a GNSS SV sample data and a second circular memory buffer to store a second GNSS signal component from the GNSS SV sample data, the first circular memory buffer and the second circular memory buffer coupled to the array processing system.

Embodiment 83. A system for processing GNSS signals, the system comprising:

a memory to store primary code seeds for GNSS signals from GNSS SVs of one or more GNSS constellations and to store a representation of primary code polynomial data for use in generating primary PRN codes for the GNSS signals;

a code generator coupled to the memory to receive the primary code seeds and the primary code polynomial data and to generate more than two primary PRN code bits in a single clock cycle during an acquisition and tracking of the GNSS signals using the primary code seeds and the primary code polynomial data.

Embodiment 84. The system as in embodiment 83 wherein the code generator generates more than two primary PRN code bits in a single clock cycle by a computation that uses a computed code advance matrix derived from an N time multiplication of a primary code polynomial matrix for a given GNSS constellation and a GNSS signal component in that GNSS constellation, wherein N represents a number of primary PRN code bits generated in a clock cycle.

Embodiment 85. The system as in embodiment 84 wherein the system generates the primary PRN code bits without storing the primary PRN code bits after tracking is completed or after DFT transformation for the present primary code epoch is completed.

Embodiment 86. The system as in embodiment 84 wherein the computed code advance matrix is precomputed before acquisition begins and is stored in the memory, and wherein N represents the amount of code advance provided by the code generator between clock cycles.

Embodiment 87. The system as in embodiment 84, the system further comprising:

a GNSS processing system coupled to the code generator, the GNSS processing system to acquire at least two of four GNSS signal components of GNSS signal by non-coherently integrating, over a period of time in an array processing system, the at least two of four GNSS signal components, the array processing system receiving GNSS sample data from a baseband memory and the GNSS sample data being formatted in a row and column array having a plurality of rows and columns.

Embodiment 88. The system as in embodiment 87 wherein the generation of GNSS PRN codes by the code generator is dynamic based on GNSS SVs in view during the acquisition and tracking of GNSS signals.

Embodiment 89. The system as in embodiment 88 wherein a GNSS primary PRN code from an output of the code generator is shifted in frequency and in time to generate a code spectrum for use in DFTs with frequency results of DFTs of received GNSS signals.

Embodiment 90. A GNSS receiver comprising:

a radiofrequency (RF) receiver that comprises at least a first RF filter and a low noise amplifier (LNA) that is tuned to only an L5 WB frequency band to receive L5 WB GNSS signals;

an analog to digital converter (ADC) coupled to the LNA to generate GNSS sample data which is stored in a baseband sample memory, wherein the RF receiver is the sole GNSS receiver in the GNSS receiver.

Embodiment 91. The GNSS receiver as in embodiment 90 wherein the RF receiver includes no amplifier for other GNSS signals outside of the L5 WB frequency band and wherein the RF receiver includes the first RF filter coupled to a GNSS antenna, and the output of the first RF filter coupled to an input of the LNA and an output of the LNA is coupled to a second RF filter.

Embodiment 92. The GNSS receiver as in embodiment 91 wherein an input of a first amplifier is coupled to an output of the second RF filter and an output of the first amplifier is coupled to the ADC and wherein the LNA and the first RF filter are disposed on a first IC and the ADC and the first amplifier are disposed on a second IC.

Embodiment 93. The GNSS receiver as in embodiment 92 wherein the GNSS receiver further comprises: a sideband split down converter that separates a GNSS sideband A sample data from a GNSS sideband B sample data; and wherein the second RF filter is disposed in the first IC.

Embodiment 94. The GNSS receiver as in embodiment 93 further comprising:

a first circular memory buffer to store the GNSS sideband A sample data; and

a second circular memory buffer to store the GNSS sideband B sample data.

Embodiment 95. The GNSS receiver as in embodiment 94 wherein the RF receiver includes no RF mixers.

Embodiment 96. The GNSS receiver as in embodiment 95 wherein the RF receiver includes no RF reference local oscillator, and wherein the GNSS antenna is tuned to only the L5 WB frequency band.

Embodiment 97. The GNSS receiver as in embodiment 95 wherein the sideband split down converter produces the GNSS sideband A sample data arranged in a first array of rows and columns and produces the GNSS sideband B sample arranged in a second array at rows and columns.

Embodiment 98. The GNSS receiver as in embodiment 95 wherein the RF receiver is tuned to receive GNSS signals centered at 1191.795 MHz and the L5 WB GNSS signals have a chipping rate of 10.23 MHz.

Embodiment 99. The GNSS receiver as in embodiment 97 wherein the GNSS antenna is the sole GNSS antenna in the GNSS receiver and wherein the RF receiver is tuned to receive GNSS signals centered at 1191.795 MHz and the L5 WB GNSS signals have a chipping rate of 10.23 MHz.

Embodiment 100. A system for processing GNSS signals, the system comprising:

an analog to digital converter (ADC) to generate a digital representation of received GNSS signals in an L5 WB GNSS frequency band;

a baseband sample memory to store the digital representation of the received GNSS signals, the baseband sample memory coupled to the ADC;

a GNSS processing system coupled to the baseband sample memory to process the digital representation of the received GNSS signals, the GNSS processing system configured to receive and process at least one of the (4) GNSS signal components of an L5 WB band GNSS signal without using L1 GNSS signals.

Embodiment 101. The system as in embodiment 100 wherein the system includes only a single GNSS antenna tuned to the L5 WB frequency band centered at 1191.795 MHz and the received GNSS signals have a chipping rate of 10.23 MHz or a chipping rate that is significantly higher (e.g., 2 times more) than the L1 GPS chipping rate of 1.023 MHz.

Embodiment 102. The system as in embodiment 101 wherein baseband sample memory stores the digital representation in an array of rows and columns arranged by rows according to a time of receipt.

Embodiment 103. The system as in embodiment 101 wherein baseband sample memory stores the digital representation in an array of rows and columns arranged by columns according to a time of receipt.

Embodiment 104. The system as in embodiment 102 wherein the GNSS processing system processes the received GNSS signals by a sequence of DFTs that includes a first set of DFTs using a decimation in time method and then a second of DFTs using a decimation in frequency method without requiring a transposition or rearrangement of data in an array containing the data.

Embodiment 105. The system as in embodiment 100 wherein an initial signal is acquired in coarse-time acquisition mode, further signals are acquired in precise-time acquisition mode, and all signals are tracked in a tracking mode.

Embodiment 106. the system as in embodiment 105 wherein acquisition-specific hardware usage is reduced while in a coherent tracking mode.

Embodiment 107. The system as in embodiment 65 wherein the GNSS processing system does not receive and acquire L1 GNSS signals.

Embodiment 108. The system as in embodiment 78 wherein the GNSS processing system does not receive and acquire L1 GNSS signals.

Embodiment 109. A GNSS receiver comprising:

an input to couple to an antenna;

an RF front end coupled to the input;

an ADC converter coupled to the RF front end;

a GNSS processing system coupled to the ADC converter, the GNSS processing system to receive GNSS signals from the ADC converter, wherein the GNSS processing system during an initial acquisition phase acquires only a selected component in the GNSS signals, the selected component having a low probability of signal change based on a coding scheme used in the selected component relative to probability of signal change for other components in the GNSS signals.

Embodiment 110. The GNSS receiver as in embodiment 109, wherein after the initial acquisition phase, the GNSS processing system acquires other components of the GNSS signals.

Embodiment 111. The GNSS receiver as in embodiment 110, wherein the selected component is an E5BI component from an SV in the Galileo constellation of GNSS satellites and the other components comprise one or more of: an E5BQ component, an E5AI component, and an E5AQ component from the same SV.

Embodiment 112. The GNSS receiver as in embodiment 110, wherein the signal change is a sign reversal in the coding scheme in the selected component.

Embodiment 113. The GNSS receiver as in embodiment 110, wherein the initial acquisition phase is one of an acquisition using coarse time or an acquisition using precise time.

Embodiment 114. The GNSS receiver as in embodiment 110, wherein the initial acquisition phase is performed after failing, for a predetermined period of time, to acquire a set of the other components of the GNSS signals.

Embodiment 115. A method of operating a GNSS receiver, the method comprising:

switching to a reduced acquisition mode in which only a selected component in GNSS signals from an SV in a GNSS constellation is acquired in an initial acquisition phase;

acquiring the selected component which has a low probability of signal change based on a coding scheme used in the selected component relative to probability of signal change for other components in the GNSS signals from the SV;

acquiring the other components after acquiring the selected component.

Embodiment 116. The method as in embodiment 115, wherein the selected component is an E5BI component from an SV in the Galileo constellation of GNSS satellites and the other components comprise one or more of: an E5BQ component, an E5AI component, and an E5AQ component from the same SV.

Embodiment 117. The method as in embodiment 116, wherein the switching occurs in response to failing, for a predetermined period of time, to acquire the other components.

Embodiment 118. A method for mitigating interference from aeronautical radio navigation (ARN) signals, the method comprising:

receiving GNSS signals and ARN signals through one or more antennas;

detecting an interference signal source having a signal strength above a noise floor, the signal source comprising ARN signals;

removing the detected interference signal source before correlation processing of the GNSS signals.

Embodiment 119. The method as in embodiment 118, wherein a predetermined threshold above the noise floor is used in the detecting of the signal source.

Embodiment 120. The method as in embodiment 118, wherein the detected signal source is removed by a Finite Impulse Response (RF) filter or an Infinite Impulse Response (IIR) filter in the frequency domain.

Embodiment 121. The method as in embodiment 118, wherein the signal source is detected by an array processor that computes discrete Fourier transforms of the GNSS signals.

Embodiment 122. A method for mitigating interference from aeronautical radio navigation (ARN) signals, the method comprising:

receiving GNSS signals from a GNSS SV and ARN signals through one or more antennas, the received GNSS signals having a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

detecting interference from a signal source from the ARN signals, the interference interfering with the first sideband but not materially interfering with the second sideband;

configuring a GNSS processing system, in response to the detected interference, to process the second sideband from the GNSS SV and not process the first sideband in order to acquire or track GNSS signals from the GNSS SV.

Embodiment 123. The method as in embodiment 122, wherein the first sideband is a higher frequency sideband and the second sideband is a lower frequency sideband.

Embodiment 124. The method as in embodiment 122, wherein the interference is detected when (1) the strength of the signal source is higher than a threshold value above a noise floor or (2) the post correlation signal to noise ratio for a particular sideband is lower than a given threshold.

Embodiment 125. The method as in embodiment 124, wherein the GNSS processing system processes the second sideband and not the first sideband during the duration of the detected interference and reverts to processing both after the interference diminishes below the noise floor.

Embodiment 126. A GNSS receiver comprising:

an input to receive GNSS signals from an antenna;

an RF front end coupled to the input to receive GNSS signals;

an RF switching mixer coupled to the RF front end;

a discrete time filter coupled to the RF switching mixer, the discrete time filter including a band pass response to select the desired GNSS signals and reject out-of-band interference and noise;

a local oscillator signal, originating at a phase lock loop (PLL) circuit, coupled to the RF switching mixer to provide a local reference signal.

Embodiment 127. The GNS receiver as in embodiment 126, wherein the discrete time filter is configured with a notch response to reject interference from aeronautical radio navigation (ARN) signals in specific locations.

Embodiment 128. The GNSS receiver as in embodiment 126, wherein the GNSS receiver further comprises: one or more direct sampling or subsampling analog to digital converters (ADCs) coupled to the discrete time filter.

Embodiment 129. The GNSS receiver as in embodiment 128, wherein a bandwidth of the discrete time filter is dynamically adjustable to switch between single or double sideband signal processing.

Embodiment 130. The GNSS receiver as in embodiment 128, wherein a clock signal, which is operatively received by the RF switching mixer and the discrete time filter, is adjustable to position a high or low sideband at baseband or at a low intermediate frequency (IF) or to position a center between the high and low sidebands at baseband or at a low intermediate frequency (IF).

Embodiment 131. The GNSS receiver as in embodiment 128, wherein the local reference signal from the PLL local oscillator is harmonically related to a sampling clock of the ADC and to the discrete time filter.

Embodiment 132. A GNSS receiver comprising:

an input to receive GNSS signals from an antenna;

an RF switching mixer coupled to the input to receive GNSS signals;

a discrete time filter coupled to the RF switching mixer;

one or more analog to digital converters (ADCs) coupled to the discrete time filter;

a phase lock loop (PLL) circuit coupled to the RF switching mixer to provide a local oscillator signal, an output of the PLL circuit being harmonically related to a sampling clock of the one or more ADCs and to a clock signal of the discrete time filter.

Embodiment 133. The GNSS receiver as in embodiment 132, wherein the one or more ADCs downconvert and provide digitalized GNSS signals.

Embodiment 134. The GNSS receiver as in embodiment 132, wherein a bandwidth of the discrete time filter is dynamically adjustable to switch between single or double sideband signal processing.

Embodiment 135. The GNSS receiver as in embodiment 132, wherein the clock signal, which is operatively received by the discrete time filter, is adjustable to position a high or low sideband at baseband or at a low intermediate frequency (IF) or to position a center between the high and low sidebands at baseband or at a low intermediate frequency (IF).

Embodiment 136. The GNSS receiver as in embodiment 132, wherein the one or more ADCs comprise an in-phase branch portion and a quadrature-phase branch portion, and wherein the quadrature-phase branch portion can be disabled, thus folding a received modulated signal on itself, and wherein dispreading operations at later stages recover original signals that existed before the folding.

Embodiment 137. A method of operating a GNSS receiver, the method comprising:

receiving GNSS signals from a GNSS SV, the GNSS signals comprising a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

selecting a first mode or a second mode of operation based upon a desired power state of the GNSS receiver;

processing, in response to selecting the first mode and while in the first mode, the first GNSS signal component in the first sideband and not processing the second GNSS signal component in the second sideband in order to acquire or track GNSS signals from the GNSS SV;

processing, in response to selecting the second mode and while in the second mode, the first GNSS signal component in the first sideband and processing the second GNSS signal component in the second sideband in order to acquire GNSS signals from the GNSS SV.

Embodiment 138. The method as in embodiment 137, wherein in the first mode, at least a portion of the GNSS receiver operates with a reduced processing rate.

Embodiment 139. The method as in embodiment 138, wherein the first mode reduces power consumption in the GNSS receiver and wherein the GNSS receiver operates in the second mode while acquiring GNSS signals and then is configured to operate in the first mode when tracking GNSS signals.

Embodiment 140. A method of operating a GNSS receiver, the method comprising:

receiving GNSS signals from a GNSS SV, the GNSS signals comprising a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

mixing the first GNSS signal component and the second GNSS signal component in a mixer to fold the first signal component and the second GNSS signal component on each other;

obtaining GNSS signals from the first GNSS signal component and the second GNSS signal component after the mixing.

Embodiment 141. A method of operating a GNSS receiver, the method comprising:

acquiring a plurality of GNSS signal components from one or more GNSS SVs during an acquisition phase;

tracking a subset of the plurality of GNSS signal components after the acquisition phase is completed.

Embodiment 142. The method as in embodiment 141, wherein the method further comprises: selecting the subset based on one or more criteria or algorithms for selecting the subset, the selecting occurring before a position of the GNSS receiver is determined.

Embodiment 143. The method as in embodiment 142, wherein the one or more criteria or algorithms provide adequate signals for tracking while reducing power consumption.

Embodiment 144. The method as in embodiment 142, wherein the one or more criteria or algorithms provide sufficient GNSS signals in order to determine a position of the GNSS receiver while reducing power consumption.

Embodiment 145. The method as in embodiment 142, wherein the plurality of GNSS signal components from one or more GNSS SVs comprise upper and lower sideband signals and wherein the subset is limited to one of the upper and lower sidebands.

Embodiment 146. A method for determining the time of arrival of a GNSS signal in which more than one Doppler hypothesis upon the received signal is required to be made, the method comprising:

performing a forward fast Fourier transform operation upon a block of signal samples to construct a frequency vector,

-   -   performing at least one of (A) circularly rotating said         frequency vector by a non-zero integer amount or (B) performing         an interpolation operation upon said frequency vector     -   to provide a first Doppler compensated frequency vector,         multiplying said first Doppler compensated frequency vector by a         first reference function vector to form a first weighted Doppler         compensated frequency vector,         and performing an inverse fast Fourier transform operation upon         the first weighted Doppler compensated frequency vector to         produce a first output time vector used to determine the time of         arrival of said GNSS signal.

Embodiment 147. The method of embodiment 146 wherein the block of signal samples is first multiplied by a complex sinusoid to frequency shifted said block of signal samples prior to performing said fast Fourier transform operation.

Embodiment 148. The method of embodiment 146 wherein the block of signal samples is first augmented with a set of zero-valued samples prior to performing said fast Fourier transform operation.

Embodiment 149. The method of embodiment 146 further comprising

performing at least one of (A) circularly rotating said frequency vector by a non-zero integer amount or (B) performing an interpolation operation upon said frequency vector

to provide a second Doppler compensated frequency vector wherein second Doppler compensated frequency vector differs from said first Doppler compensated frequency vector, multiplying said second Doppler compensated frequency vector by the first reference function vector to form a second weighted Doppler compensated frequency vector, and performing an inverse fast Fourier transform operation upon the second weighted Doppler compensated frequency vector to produce a second output time vector used to determine the time of arrival of said GNSS signal.

Embodiment 150. The method of embodiment 146 further comprising

multiplying said first Doppler compensated frequency vector by a second reference function vector to form a second weighted Doppler compensated frequency vector,

wherein said second reference function vector differs from said first reference function vector, and performing an inverse fast Fourier transform operation upon the second weighted Doppler compensated frequency vector to produce a second output time vector used to determine the time of arrival of a GNSS signal.

Embodiment 151. The method of embodiment 146 further comprising

performing at least one of (A) circularly rotating said frequency vector by a non-zero integer amount or (B) performing an interpolation operation upon said frequency vector

to provide a second Doppler compensated frequency vector wherein second Doppler compensated frequency vector differs from said first Doppler compensated frequency vector,

multiplying said second Doppler compensated frequency vector by a second reference function vector to form a second weighted Doppler compensated frequency vector, wherein said second reference function vector differs from said first reference function vector,

and performing an inverse fast Fourier transform operation upon the second weighted Doppler compensated frequency vector to produce a second output time vector used to determine the time of arrival of said GNSS signal.

Embodiment 152. A method for determining the time of arrival of a GNSS signal in which more than one Doppler hypothesis upon the received signal is required to be made, the method comprising:

performing a forward fast Fourier transform operation upon a block of signal samples to construct a frequency vector,

performing at least one of (A) circularly rotating a first reference function vector by a non-zero integer amount or (B) performing an interpolation operation upon said reference function vector, to provide a first Doppler compensated reference function vector, multiplying said first Doppler compensated reference function vector by said frequency vector to form a first weighted Doppler compensated frequency vector,

and performing an inverse fast Fourier transform operation upon the first weighted Doppler compensated frequency vector to produce a first output time vector used to determine the time of arrival of said GNSS signal.

Embodiment 153. The method of embodiment 152 wherein the block of signal samples is first multiplied by a complex sinusoid to frequency shifted said block of signal samples prior to performing said fast Fourier transform operation.

Embodiment 154. The method of embodiment 152 wherein the block of signal samples is first augmented with a set of zero-valued samples prior to performing said fast Fourier transform operation.

Embodiment 155. The method of embodiment 152 further comprising performing at least one of (A) circularly rotating said first reference function vector by a non-zero integer amount or (B) performing an interpolation operation upon said reference function vector,

to provide a second Doppler compensated reference function vector, wherein said second Doppler compensated reference function vector differs from said first Doppler compensated reference function vector;

multiplying said second Doppler compensated reference function vector by said frequency vector to form a second weighted Doppler compensated frequency vector,

and performing an inverse fast Fourier transform operation upon the second weighted Doppler compensated frequency vector to produce a second output time vector used to determine the time of arrival of said GNSS signal.

Embodiment 156. The method of embodiment 152 further comprising

performing at least one of (A) circularly rotating a second reference function vector by a non-zero integer amount or (B) performing an interpolation operation upon a second reference function vector to provide a second Doppler compensated reference function vector wherein said second reference function vector differs from said first reference function vector;

multiplying said second Doppler compensated reference function vector by said frequency vector to form a second weighted Doppler compensated frequency vector, and performing an inverse fast Fourier transform operation upon the second weighted Doppler compensated frequency vector to produce a second output time vector used to determine the time of arrival of a GNSS signal.

Embodiment 157. The method of embodiment 152 further comprising

performing at least one of (A) circularly rotating a second reference function vector by a non-zero integer amount or (B) performing an interpolation operation upon said reference function vector, to provide a second Doppler compensated reference function vector,

wherein said second Doppler compensated reference function vector differs from said first Doppler compensated frequency vector, wherein said second reference function vector differs from said first reference function vector,

multiplying said second Doppler compensated reference function vector by said frequency vector to form a second weighted Doppler compensated frequency vector, and performing an inverse fast Fourier transform operation upon the second weighted Doppler compensated frequency vector to produce a second output time vector used to determine the time of arrival of said GNSS signal.

Embodiment 158. A method for determining the time of arrival of a GNSS signal in which more than one Doppler hypothesis upon the received signal is required to be made, the method comprising:

performing a forward fast Fourier transform operation upon a block of signal samples to construct a frequency vector;

performing at least one of (A) circularly rotating said frequency vector by a non-zero integer amount or (B) performing an interpolation operation upon said frequency vector

to provide a first Doppler compensated frequency vector;

performing at least one of (A) circularly rotating a first reference function vector by a non-zero integer amount or (B) performing an interpolation operation upon said reference function vector, to provide a first Doppler compensated reference function vector;

multiplying said first Doppler compensated frequency vector by a said first Doppler compensated reference function vector to form a first weighted Doppler compensated frequency vector;

and performing an inverse fast Fourier transform operation upon the first weighted Doppler compensated frequency vector to produce a first output time vector used to determine the time of arrival of said GNSS signal.

Embodiment 159. The method of Embodiment 158 further comprising performing at least one of (A) circularly rotating said frequency vector by a non-zero integer amount or (B) performing an interpolation operation upon said frequency vector to provide a second Doppler compensated frequency vector;

performing at least one of (A) circularly rotating a second reference function vector by a non-zero integer amount or (B) performing an interpolation operation upon said second reference function vector, to provide a second Doppler compensated reference function vector;

multiplying said first Doppler compensated frequency vector by a said first Doppler compensated reference function vector to form a second weighted Doppler compensated frequency vector, wherein the second weighted Doppler compensated frequency vector differs from said first weighted Doppler compensated frequency vector; and

performing an inverse fast Fourier transform operation upon the second weighted Doppler compensated frequency vector to produce a second output time vector used to determine the time of arrival of said GNSS signal.

A machine readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer or processing logic implemented in hardware). For example, a machine readable medium includes read only memory (“ROM”); random access memory (“RAM”) such as Dynamic Random Access Memory; magnetic disk storage media; optical storage media; flash memory devices; etc.

An article of manufacture may be used to store program code. An article of manufacture that stores program code may be embodied as, but is not limited to, one or more memories (e.g., one or more flash memories, random access memories (static, dynamic or other)), optical disks, CD-ROMs, DVD ROMs, EPROMs, EEPROMs, magnetic or optical cards or other type of machine-readable media suitable for storing electronic instructions. Program code may also be downloaded from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a propagation medium (e.g., via a communication link (e.g., a network connection)). Processing logic, such as one or more hardware processing systems (e. g., a microprocessor or microcontroller, etc.) can execute the program code to cause a data processing system to perform a method of one or more of the embodiments described herein.

In the foregoing specification, specific exemplary embodiments have been described. It will be evident that various modifications may be made to those embodiments without departing from the broader spirit and scope set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. 

What is claimed is:
 1. A system for processing GNSS signals, said system comprising: a radiofrequency analog to digital converter (ADC) to generate a digital representation of received GNSS signals; a baseband sample memory to store the digital representation of the received GNSS signals as digitized GNSS sample data, the baseboard sample memory configured to store an array of the digitized GNSS sample data in N2 rows and N1 columns, the digitized GNSS sample data in the array being stored in row order in the baseband sample memory and N2 being larger than N1, the row order containing the digitized GNSS sample data that was received over a time period that includes a first time period and a second time period such that a first row in the row order contains digitized GNSS sample data received during the first time period and a second row, which follows the first row in the row order, contains digitized GNSS sample data received during the second time period that follows, in time, the first time period, the baseband sample memory coupled to the radiofrequency ADC; a set of arithmetic logic units (ALU) configured to perform discrete Fourier transform (DFT) operations, the set of ALUs coupled to the baseband sample memory, the set of ALUs configured to perform, in parallel and concurrently in time, N1 DFTs, wherein each of the N1 DFTs contains N2 points in the DFT and the outputs of the N1 DFTs are stored in a partial result sample array, and wherein the set of ALUs are configured to then perform N2 DFTs, each of the N2 DFTs containing N1 points from the partial result sample array, the N2 DFTs providing an output stored in an DFT result array that is arranged in column order.
 2. The system as in claim 1 wherein the baseband sample memory is configured as a circular memory buffer that stores the array.
 3. The system as in claim 2 wherein the N1 DFTs use the same operations and same program control instructions for the set of ALUs to operate on different data.
 4. The system as in claim 3 wherein the N2 DFTs are performed consecutively over time and wherein the circular memory buffer stores more than one frame of pseudorandom GNSS codes which is more than 1 millisecond.
 5. The system as in claim 3 wherein the N1 DFTs and the N2 DFTs use a decimation in time method and wherein N1 is one of the integer values: 5 or 10 or 20 or
 40. 6. The system as in claim 3 wherein a change from row order to column order avoids a re-ordering algorithm, the change produced by a combination of the N1 DFTs followed by the N2 DFTs.
 7. The system as in claim 3 wherein a GNSS code generator is configured to generate a GNSS code, and the set of ALUs performs a set of DFTs on the GNSS code to provide a code spectrum result data stored in a code spectrum memory in a column order, the code spectrum result data including GNSS PRN code data that is frequency and/or time shifted.
 8. The system as in claim 7 wherein the set of ALUs is configured to multiply the code spectrum result data by the output stored in the DFT result array to produce a product array.
 9. The system as in claim 8 wherein the set of ALUs is configured to perform an inverse DFT on the product array using a decimation in frequency method.
 10. The system as in claim 9 wherein the inverse DFT comprises: (1) in a first stage, N2 DFTs with conjugated inputs, each of the N2 DFTs containing N1 points, and (2) in a second stage that follows the first stage, N1 DFTs, each of the N1 DFTs containing N2 points.
 11. The system as in claim 2 wherein the baseband sample memory is a dual port memory.
 12. The system as in claim 7 wherein the GNSS code generator generates a pseudorandom code for each GNSS SV in view every millisecond when it is needed during an acquisition phase and does not store a generated pseudorandom code after it is used, and the generated pseudorandom code is used to generate the GNSS code spectrum.
 13. The system as in claim 12 wherein the GNSS code spectrum is aligned in place in memory in both frequency and phase to match code phase and frequency shift hypotheses associated with the received GNSS signals.
 14. The system as in claim 13 wherein the alignment is performed by CORDIC hardware.
 15. A system as in claim 1 in which the digitized GNSS sample data is stored in column order rather than row order.
 16. A system for processing GNSS L5 band signals, the system comprising: a radiofrequency analog to digital converter (ADC) to generate a digital representation of received GNSS signals; a baseband sample memory to store the digital representation of the received GNSS signals, the baseband sample memory coupled to the ADC; a GNSS processing system coupled to the baseband sample memory to process the digital representation of the received GNSS signals, the GNSS processing system configured to process four (4) GNSS signal components of a GNSS signal to non-coherently integrate all four GNSS signal components to generate and store the non-coherent integration data for each of the four GNSS signal components into a single hypothesis memory to acquire GNSS signals.
 17. The system as in claim 16 wherein the single hypothesis memory is less than 2 megabytes of memory and wherein the four GNSS signal components include a Galileo E5AI signal component, a Galileo E5BI signal component, a Galileo E5BQ signal component, and a Galileo E5AQ signal component or four GNSS signal components used in a Beidou/Compass B2 system or both of the Galileo E5 and Beidou/Compass B2 signal components.
 18. The system as in claim 17 wherein the GNSS processing system processes received GNSS signal from at least two GNSS constellations including: the Galileo E5 constellation of GNSS SVs; an L5 GPS constellation of GNSS SVs, a Glonass K2 constellation of GNSS SVs, a QZSS constellation of GNSS SVs, and a Beidou B2 constellation of GNSS SVs.
 19. The system as in claim 16 further comprising: a code generator to generate GNSS PRN codes during acquisition and tracking of GNSS signals without storing the GNSS PRN codes after tracking is completed.
 20. The system as in claim 19 wherein the code generator generates more than two primary PRN code bits in a clock cycle during the acquisition and tracking.
 21. The system as in claim 20 wherein the code generator generates the more than two primary PRN code bits in a clock cycle by a computation that uses a computed code advance matrix derived from an N times multiplication of a code polynomial matrix for a given GNSS constellation and GNSS signal component in that GNSS constellation, N representing a number of primary PRN code bits generated in a clock cycle.
 22. The system as in claim 21 wherein the GNSS processing system shares a memory with one or more processors, and the GNSS processing system, the cache memory and the one or more application processors are all disposed on a same single integrated circuit.
 23. The system as in claim 22 wherein the GNSS processing system includes an acquisition engine and a tracking engine, and the acquisition engine includes processing logic to receive an array of GNSS sample data, arranged, according to time of receipt, in either row order or column order, and the processing logic to perform DFTs using a decimation in time algorithm on the array of GNSS sample data to produce frequency domain results that are multiplied by a code spectrum of GNSS PRN codes for GNSS SVs in view, and the resulting product of the frequency domain results and the code spectrum is then processed in the processing logic by IDFTs using a decimation in frequency algorithm to produce hypotheses of possible acquired GNSS signals that are accumulated non-coherently in the single hypothesis memory.
 24. The system as in claim 23 wherein the array of GNSS sample data is stored in two circular memory buffers that comprise a first circular memory buffer to store A-band GNSS sample data and a second circular memory buffer to store B-band GNSS sample data, wherein a plurality of GNSS constellations may be received in at least one said band.
 25. The system as in claim 21 wherein a GNSS primary PRN code from an output of the code generator is shifted in frequency and is shifted in time before applying a set of DFTs using a decimation in time algorithm to generate a code spectrum that is multiplied by frequency domain results from a set of DFTs, using a decimation in time algorithm, on a received GNSS signal.
 26. The system as in claim 24 wherein a GNSS primary PRN code from an output of the code generator is shifted in frequency and is shifted in time to generate the code spectrum.
 27. The system as in claim 23 wherein an order in the array changes through a sequence of the DFTs such that no transposing or rearranging of data is required when the IDFTs are performed.
 28. The system as in claim 27 wherein the sequence of DFTs avoids using memory or processing resources that would be used for the transposing or rearranging.
 29. A system for processing GNSS signals, the system comprising: a memory to store primary code seeds for GNSS signals from GNSS SVs of one or more GNSS constellations and to store a representation of primary code polynomial data for use in generating primary PRN codes for the GNSS signals; a code generator coupled to the memory to receive the primary code seeds and the primary code polynomial data and to generate more than two primary PRN code bits in a single clock cycle during an acquisition and tracking of the GNSS signals using the primary code seeds and the primary code polynomial data.
 30. The system as in claim 29 wherein the code generator generates more than two primary PRN code bits in a single clock cycle by a computation that uses a computed code advance matrix derived from an N time multiplication of a primary code polynomial matrix for a given GNSS constellation and a GNSS signal component in that GNSS constellation, wherein N represents a number of primary PRN code bits generated in a clock cycle.
 31. The system as in claim 30 wherein the system generates the primary PRN code bits without storing the primary PRN code bits after tracking is completed or after DFT transformation for the present primary code epoch is completed.
 32. The system as in claim 30 wherein the computed code advance matrix is precomputed before acquisition begins and is stored in the memory, and wherein N represents the amount of code advance provided by the code generator between clock cycles.
 33. The system as in claim 30, the system further comprising: a GNSS processing system coupled to the code generator, the GNSS processing system to acquire at least two of four GNSS signal components of GNSS signal by non-coherently integrating, over a period of time in an array processing system, the at least two of four GNSS signal components, the array processing system receiving GNSS sample data from a baseband memory and the GNSS sample data being formatted in a row and column array having a plurality of rows and columns.
 34. The system as in claim 33 wherein the generation of GNSS PRN codes by the code generator is dynamic based on GNSS SVs in view during the acquisition and tracking of GNSS signals.
 35. The system as in claim 34 wherein a GNSS primary PRN code from an output of the code generator is shifted in frequency and in time to generate a code spectrum for use in DFTs with frequency results of DFTs of received GNSS signals. 